ABSTRACT
The power distribution network of an integrated circuit must be checked throughout the design process to ensure that supply voltage fluctuations do not exceed certain critical thresholds. One way of doing this is by simulation, which requires knowledge of the circuit currents that load the grid. These currents are hard to specify. In many cases, and certainly during early power grid design, they may be simply unknown because the circuit itself may not yet be specified. Vectorless verification refers to the class of techniques, developed over the last 12 years, for verifying the grid in the absence of complete information about the circuit currents.
- R. Chaudhry, D. Blaauw, R. Panda, and T. Edwards, "Current signature compression for IR-drop analysis," in Design Automation Conference, Los Angeles, CA, June 5--9 2000, pp. 162--167. Google ScholarDigital Library
- S. Pant and E. Chiprout, "Power grid physics and implications for CAD," in ACM/IEEE 43rd Design Automation Conference (DAC-06), San Francisco, CA, July 24--28 2006, pp. 199--204. Google ScholarDigital Library
- M. Avci and F. N. Najm, "Early P/G grid voltage integrity verification," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 7--11 2010, pp. 816--823. Google ScholarDigital Library
- F. N. Najm, Circuit Simulation. Hoboken, NJ: John Wiley & Sons, Inc., 2010. Google ScholarDigital Library
- D. Kouroussis and F. N. Najm, "A static pattern-independent technique for power grid voltage integrity verification," in ACM/IEEE 40th Design Automation Conference (DAC-03), Anaheim, CA, June 2--6 2003, pp. 99--104. Google ScholarDigital Library
- D. Kouroussis, I. A. Ferzli, and F. N. Najm, "Incremental partitioning-based vectorless power grid verification," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD-05), San Jose, CA, November 6--10 2005, pp. 358--364. Google ScholarDigital Library
- Abhishek and F. N. Najm, "Incremental power grid verification," in ACM/IEEE 49th Design Automation Conference (DAC-2012), San Francisco, CA, June 3--7 2012, pp. 151--156. Google ScholarDigital Library
- A. Goyal and F. N. Najm, "Efficient RC power grid verification using node elimination," Design, Automation and Test in Europe (DATE-11), pp. 257--260, March 14--18 2011.Google Scholar
- N. Abdul Ghani and F. N. Najm, "Power grid verification using node and branch dominance," in ACM/IEEE 48th Design Automation Conference (DAC-2011), San Diego, CA, June 5--9 2011, pp. 682--687. Google ScholarDigital Library
- I. A. Ferzli, F. N. Najm, and L. Kruse, "A geometric approach for early power grid verification using current constraints," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 5--8 2007, pp. 40--47. Google ScholarDigital Library
- S. Lang, Algebra. Menlo Park, CA: Addison-Wesley, 1993.Google Scholar
- Y. Saad, Iterative Methods for Sparse Linear Systems. Philadelphia, PA: SIAM, 2003. Google ScholarDigital Library
- S. Demko, W. F. Moss, and P. W. Smith, "Decay rates for inverses of band matrices," Mathematics of computation, vol. 43, no. 168, pp. 491--499, Oct. 1984.Google ScholarCross Ref
- M. J. Grote and T. Huckle, "Parallel preconditioning with sparse approximate inverses," SIAM Journal on Scientific Computing, vol. 18, no. 3, pp. 838--853, May 1997. Google ScholarDigital Library
- N. H. Abdul Ghani and F. N. Najm, "Fast vectorless power grid verification using an approximate inverse technique," in ACM/IEEE 46th Design Automation Conference (DAC-09), San Francisco, CA, July 26--31 2009, pp. 184--189. Google ScholarDigital Library
- T.-H. Chen, C. Luk, and C. C.-P. Chen, "INDUCTWISE: inductance-wise interconnect simulator and extractor," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 7, pp. 884--894, Jul. 2003. Google ScholarDigital Library
- N. H. Abdul Ghani and F. N. Najm, "Fast vectorless power grid verification under an RLC model," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 691--703, May 2011. Google ScholarDigital Library
- I. A. Ferzli, E. Chiprout, and F. N. Najm, "Verification and codesign of the package and die power delivery system using wavelets," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 92--102, Jan. 2010. Google ScholarDigital Library
- X. Xiong and J. Wang, "Dual algorithms for vectorless power grid verification under linear current constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 10, pp. 1469--1482, Oct. 2011. Google ScholarDigital Library
- X. Xiong and J. Wang, "A hierarchical matrix inversion algorithm for vectorless power grid verification," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 7--11 2010, pp. 543--550. Google ScholarDigital Library
- X. Xiong and J. Wang, "Vectorless verification of RLC power grids with transient current constraints," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 7--10 2011, pp. 548--554. Google ScholarDigital Library
- M. Avci, "Early dual grid voltage integrity verification," Master's thesis, University of Toronto, Toronto, Ontario, Canada, 2010.Google Scholar
- Y. Wang, X. Hu, C.-K. Cheng, G.-K.-H. Pang, and N. Wong, "A realistic early-stage power grid verification algorithm based on hierarchical constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 1, pp. 109--120, Jan. 2012. Google ScholarDigital Library
- Y. Wang, X. Hu, C.-K. Cheng, G.-K.-H. Pang, and N. Wong, "Corrigendum to "A realistic early-stage power grid verification algorithm based on hierarchical constraints"," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 3, pp. 452--452, Mar. 2012. Google ScholarDigital Library
Index Terms
- Overview of vectorless/early power grid verification
Recommendations
Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification
With the current aggressive integrated circuit technology scaling, vectorless power grid voltage integrity verification becomes key to designing reliable power delivery networks. To address the challenges of existing vectorless power grid verification ...
Transient Noise Bounds using Vectorless Power Grid Verification
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided DesignEfficient power grid verification, critical in modern integrated circuits, is computationally demanding because of increasing grid sizes. Vectorless approach to grid verification estimates worst-case voltage noises without detailed evaluation of load ...
Scalable vectorless power grid current integrity verification
DAC '13: Proceedings of the 50th Annual Design Automation ConferenceTo deal with the growing phenomenon of electromigration (EM), power grid current integrity verification becomes indispensable to designing reliable power delivery networks (PDNs). Unlike previous works that focus on vectorless voltage integrity ...
Comments