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Fast approximation for peak power driven voltage partitioning in almost linear time

Published: 05 November 2012 Publication History

Abstract

Voltage partitioning on functional units/blocks targeting peak power minimization has been demonstrated to be effective for energy reduction considering voltage island shutdown impact. However, the existing technique can only solve this NP-hard problem efficiently on small designs. In this paper, a much faster linear time approximation scheme is proposed, which can approximate the optimal voltage partitioning solution within a factor 1 + ε, for any 0 < ε < 1, and runs in O(n + 1/εO(1)) time, where n is the number of functional units. There are multiple ingredients in such a surprisingly low time complexity algorithm. It first categorizes all the functional units into big functional units and small functional units using an ε related threshold. Subsequently, a rounding based dynamic programming procedure is performed to handle big functional units and a linear programming based algorithm is performed to handle small functional units, which is followed by the discretization of the continuous linear programming solution. Moreover, through the exploration of the unique nature of our problem, a greedy algorithm is proposed to optimally solve the linear programming formulation in a combinatorial fashion. Further, since patching a salient partitioning solution of big functional units with that of small functional units could lead to a much worse combined solution, a highly efficient enumeration process running in time independent of n is proposed. The experimental results demonstrate that our algorithm runs very fast. It needs only 0.3 second to partition a testcase with 5000 functional units which is more than 10000X faster than the existing algorithm while still reducing the peak power by 7.4%.

References

[1]
R. Shelar and M. Patyra, "Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor," in Proceedings of ACM International Symposium on Physical Design, 2010.
[2]
D. Lackey, P. Zuchowski, T. Bednar, D. Stout, S. Gould, and J. Cohn, "Managing Power and Performance for System-on-Chip Designs Using Voltage Islands," in Proccedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 195--202, 2002.
[3]
Z. Gu, Y. Yang, J. Wang, R. Dick, and L. Shang, "Taphs: Thermal-Aware Unified Physical-Level and High-Level Synthesis," in Proceedings of IEEE Asia and South Pacific Design Automation Conference, pp. 879--885, 2006.
[4]
H.-Y. Liu, W.-P. Lee, and Y.-W. Chang, "A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages," in Proceedings of IEEE/ACM Design Automation Conference, pp. 887--890, 2007.
[5]
T. Lin, S. Dong, B. Yu, S. Chen and S. Goto, "A revisit to voltage partitioning problem", in Proceedings of the IEEE/ACM Symposium on Great Lakes Symposium on VLSI, pp. 115--118, 2010.
[6]
M. Hamada, Y. Ootaguro, and T. Kuroda, "Utilizing Surplus Timing for Power Reduction," in Proceedings of IEEE Conference on Custom Integrated Circuits, pp. 89--92, 2001.
[7]
J. Wang and S. Hu, "The Fast Optimal Voltage Partitioning Algorithm For Peak Power Density Minimization", in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2010.
[8]
J. Wang, X. Chen, C. Liao and S. Hu, "The Approximation Scheme For Peak Power Driven Voltage Partitioning", in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2011.
[9]
H. Kellerer and U. Pferschy, A New Fully Polynomial Time Approximation Scheme for the Knapsack Problem, Journal of Combinatorial Optimization, Vol. 3, No. 1, pp. 59--71, 1999.

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cover image ACM Conferences
ICCAD '12: Proceedings of the International Conference on Computer-Aided Design
November 2012
781 pages
ISBN:9781450315739
DOI:10.1145/2429384
  • General Chair:
  • Alan J. Hu
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2012

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Author Tags

  1. energy efficiency
  2. linear time approximation scheme
  3. peak power
  4. voltage partitioning

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