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Power minimization for dynamically reconfigurable FPGA partitioning

Published: 29 March 2013 Publication History

Abstract

Dynamically reconfigurable FPGA (DRFPGA) implements a given circuit system by partitioning it into stages and then executing each stage sequentially. Traditionally, the number of communication buffers is minimized. In this article, we study the partitioning problem targeting at power minimization for the DRFPGAs that have lookup table (LUT) based logic blocks. We analyze the power consumption caused by the communication buffers in the temporal partitioning. Based on the analysis, we use a flow network to represent a given circuit so that the power consumption of buffers is correctly evaluated and the temporal constraints are satisfied in circuit partitioning. The well known flow-based FBB algorithm is then applied to the network to find the area-balanced partitioning of minimum power consumption. Experimental results show that our method outperforms the conventional partitioning algorithms in terms of power consumption. The problem is then extended to include constraints on the number of communication buffers. We provide a net modeling for this extended problem and present an extension of the FBB algorithm to obtain a power-optimal solution. Experimental results demonstrate the effectiveness of the proposed algorithm in reducing power consumption as compared to the previous partitioning algorithms without exceeding the buffer number limit.

References

[1]
Bhat, N. B., Chaudhary, K., and Kuh, E. S. 1993. Performance-oriented fully routable dynamic architecture for a field programmable logic device. Memo no. UCB/RELM93/42, University of California, Berkeley.
[2]
Brown, J., Chen, D., Eslick, I., Tau, E., and DeHon, A. 1995. DELTA: Prototype for a First-Generation Dynamically Programmable Gate Array. MIT Press, Cambridge, MA.
[3]
Chang, D. and Marek-Sadowska, M. 1997. Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays. 142--148.
[4]
Chang, D. and Marek-Sadowska, M. 1999. Partitioning sequential circuits on dynamically reconfigurable FPGAs. IEEE Trans. Computers 48, 6, 565--578.
[5]
Chao, M. C. T., Wu, G. M., Jiang, I. H. R., and Chang, Y. W. 1999. A clustering- and probability-based approach for time-multiplexed FPGA partitioning. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 364--368.
[6]
Cheng, L., Li, F., Lin, Y., Wong, P., and He, L. 2007. Device and architecture cooptimization for FPGA power reduction. IEEE Trans. Comput.-Aid. Des. Integrat. Circuits Syst. 26, 7, 1211--1221.
[7]
Chiricescu, S., Leeser, M., and Vai, M. M. 2001. Design and analysis of a dynamically reconfigurable three-dimensional FPGA. IEEE Trans. VLSI Syst. 9, 1, 186--196.
[8]
DeHon, A. 1994. DPGA-coupled microprocessors: commodity ICs for the early 21st century. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines. 31--39.
[9]
Farrahi, A. H. and Sarrafzadeh, M. 1994. FPGA technology mapping for power minimization. In Proceedings of the International Workshop on Field Programmable Logic and Applications. 66--77.
[10]
Ford, J. R. and Fulkerson, D. R. 1962. Flows in Networks. Princeton University Press, Princeton, NJ.
[11]
Fujii, T., Furuta, K.-I., Motomura, M., Nomura, M., Mizuno, M., Anjo, K.-I., Wakabayashi, K., Hirota, Y., Nakazawa, Y.-E., Ito, H., and Yamashina, M. 1999. A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture. In Proceedings of the IEEE International Solid-State Circuits Conference. 364--365.
[12]
Huang, C. and Vahid, F. 2010. Server-side coprocessor updating for mobile devices with FPGAs. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 125--134.
[13]
Jones, D. and Lewis, D. M. 1995. A time-multiplexed FPGA architecture for logic emulation. In Proceedings of the IEEE Custom Integrated Circuits Conference. 495--498.
[14]
Kotani, K., Miyamoto, N., Ohkawa, T., Jamak, A., Kita S., and Ohmi, T. 2005. A personal-use single-chip emulator using dynamically reconfigurable logic array. In Proceedings of the IEEE Asian Solid-State Circuits Conference. 329--332.
[15]
Li, H., Katkoori, S., and Mak, W. K. 2004. Power minimization algorithms for LUT-based FPGA technology mapping. ACM Trans. Desi. Autom. Electron. Syst. 9, 1, 33--51.
[16]
Liu, H. and Wong, D. F. 1998a. Network flow based circuit partitioning for time-multiplexed FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 497--504.
[17]
Liu, H. and Wong, D. F. 1998b. Network-flow-based multiway partitioning with area and pin constraints. IEEE Trans. Comput.-Aid. Desi. Integrat. Circuits Syst. 17, 1, 50--59.
[18]
Mak, W. K. and Young, E. F. Y. 2003. Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. Comput.-Aid. Desi. Integrat. Circuits Syst. 22, 7, 952--959.
[19]
Najm, F. N. 1993. Transition density: a new measure of activity in digital circuits. IEEE Trans. Comput.-Aid. Desi. Integrat. Circuits Syst. 12, 2, 310--323.
[20]
Meribout, M. and Motomura, M. 2004. A combined approach to high-level synthesis for dynamically reconfigurable systems. IEEE Trans. Computers 53, 12, 1508--1522.
[21]
Pantonial, R., Khan, M. A., Miyamoto, N., Kotani, K., Sugawa, S., and Ohmi, T. 2007. Improving execution speed of FPGA using dynamically reconfigurable technique. In Proceedings of the Asia and South Pacific Design Automation Conference. 108--109.
[22]
Saxena, V., Najm, F. N., and Hajj, I. N. 2002. Estimation of state line statistics in sequential circuits. ACM Trans. Desi. Autom. Electron. Syst. 7, 3, 455--473.
[23]
Trimberger, S. 1998. Scheduling designs into a time-multiplexed FPGA. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 153--160.
[24]
Trimberger, S., Carberry, D., Johnson, A., and Wong, J. 1997. A time-multiplexed FPGA. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines. 22--28.
[25]
Wang, Z. H., Liu, E. C., Lai, J., and Wang, T. C. 2001. Power minimization in LUT-based FPGA technology mapping. In Proceedings of the Asia South Pacific Design Automation Conference. 635--640.
[26]
Weste, N. and Eshraghian, K. 1993. Principles of CMOS VLSI Design: A Systems Perspective. Addison-Wesley, Reading, MA.
[27]
Wu, G. M., Lin, J. M., and Chang, Y. W. 2001. Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. Comput.-Aid. Desi. Integrat. Circuits Syst. 20, 10, 1266--1274.
[28]
Yang, H. and Wong, D. F. 1996. Efficient network flow based min-cut balanced partitioning. IEEE Trans. Comput.-Aid. Desi. Integrat. Circuits Syst. 15, 12, 1533--1540.

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  • (2016)Energy-Aware Service Orchestration Based on Temporal Reconfigurable Architecture2016 IEEE 25th International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE)10.1109/WETICE.2016.23(68-70)Online publication date: Jun-2016
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  • (2016)OaaS Based on Temporal Partitioning with Minimum Energy ConsumptionProcedia Computer Science10.1016/j.procs.2016.08.23296:C(540-549)Online publication date: 1-Oct-2016

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cover image ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems  Volume 12, Issue 1s
Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
March 2013
701 pages
ISSN:1539-9087
EISSN:1558-3465
DOI:10.1145/2435227
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 29 March 2013
Accepted: 01 February 2011
Revised: 01 November 2010
Received: 01 July 2010
Published in TECS Volume 12, Issue 1s

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Author Tags

  1. Dynamically reconfigurable FPGA
  2. power optimization
  3. reconfigurable computing
  4. temporal partitioning

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View all
  • (2016)Energy-Aware Service Orchestration Based on Temporal Reconfigurable Architecture2016 IEEE 25th International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE)10.1109/WETICE.2016.23(68-70)Online publication date: Jun-2016
  • (2016)Energy Efficient Partitioning and Scheduling Approach for Scientific Workflows in the Cloud2016 IEEE International Conference on Services Computing (SCC)10.1109/SCC.2016.26(146-154)Online publication date: Jun-2016
  • (2016)OaaS Based on Temporal Partitioning with Minimum Energy ConsumptionProcedia Computer Science10.1016/j.procs.2016.08.23296:C(540-549)Online publication date: 1-Oct-2016

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