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Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers

Published: 11 February 2013 Publication History

Abstract

The rising complexity of verification has led to an increase in the use of FPGA prototyping, which can run at significantly higher operating frequencies and achieve much higher coverage than logic simulations. However, a key challenge is observability into these devices, which can be solved by embedding trace-buffers to record on-chip signal values. Rather than connecting a predetermined subset of circuits signals to dedicated trace-buffer inputs at compile-time, in this work we propose that a virtual overlay network is built to multiplex all on-chip signals to all on-chip trace-buffers. Subsequently, at debug-time, the designer can choose a signal subset for observation. To minimize its overhead, we build this network out of unused routing multiplexers, and by using optimal bipartite graph matching techniques, we show that any subset of on-chip signals can be connected to 80-90% of the maximum trace-buffer capacity in less than 50 seconds.

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    cover image ACM Conferences
    FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
    February 2013
    294 pages
    ISBN:9781450318877
    DOI:10.1145/2435264
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    Publication History

    Published: 11 February 2013

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    Author Tags

    1. FPGA debug
    2. FPGA prototyping
    3. overlay network
    4. trace-buffers
    5. verification

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    • (2021)XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM51124.2021.00009(1-9)Online publication date: May-2021
    • (2019)Preallocating Resources for Distributed Memory Based FPGA Debug2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00067(384-390)Online publication date: Sep-2019
    • (2019)An Integrated on-Silicon Verification Method for FPGA OverlaysJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05786-z35:2(173-189)Online publication date: 1-Apr-2019
    • (2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
    • (2018)Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00022(81-813)Online publication date: Aug-2018
    • (2018)An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded ProcessorsApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_35(433-445)Online publication date: 8-Apr-2018
    • (2017)BitManProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130592(894-897)Online publication date: 27-Mar-2017
    • (2017)BITMAN: A tool and API for FPGA bitstream manipulationsDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927114(894-897)Online publication date: Mar-2017
    • (2017)Access Network Generation for Efficient Debugging of FPGAsProceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3120895.3120920(1-6)Online publication date: 7-Jun-2017
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