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Word-length optimization beyond straight line code

Published: 11 February 2013 Publication History

Abstract

The silicon area benefits that result from word-length optimization have been widely reported by the FPGA community. However, to date, most approaches are restricted to straight line code, or code that can be converted into straight line code using techniques such as loop-unrolling. In this paper, we take the first steps towards creating analytical techniques to optimize the precision used throughout custom FPGA accelerators for algorithms that contain loops with data dependent exit conditions. To achieve this, we build on ideas emanating from the software verification community to prove program termination. Our idea is to apply word-length optimization techniques to find the minimum precision required to guarantee that a loop with data dependent exit conditions will terminate. Without techniques to analyze algorithms containing these types of loops, a hardware designer may elect to implement every arithmetic operator throughout a custom FPGA-based accelerator using IEEE-754 standard single or double precision arithmetic. With this approach, the FPGA accelerator would have comparable accuracy to a software implementation. However, we show that using our new technique to create custom fixed and floating point designs, we can obtain silicon area savings of up to 50% over IEEE standard single precision arithmetic, or 80% over IEEE standard double precision arithmetic, at the same time as providing guarantees that the created hardware designs will work in practice.

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Cited By

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  • (2019)Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH.2019.00040(175-182)Online publication date: Jun-2019
  • (2017)Algorithms and Arithmetic: Choose Wisely2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH.2017.17(142-143)Online publication date: Jul-2017
  • (2017)Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converterInternational Journal of Circuit Theory and Applications10.1002/cta.232345:11(1701-1741)Online publication date: Feb-2017
  • Show More Cited By

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    cover image ACM Conferences
    FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
    February 2013
    294 pages
    ISBN:9781450318877
    DOI:10.1145/2435264
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 February 2013

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    Author Tags

    1. loop termination
    2. precision analysis
    3. word-length optimization

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    View all
    • (2019)Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers2019 IEEE 26th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH.2019.00040(175-182)Online publication date: Jun-2019
    • (2017)Algorithms and Arithmetic: Choose Wisely2017 IEEE 24th Symposium on Computer Arithmetic (ARITH)10.1109/ARITH.2017.17(142-143)Online publication date: Jul-2017
    • (2017)Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converterInternational Journal of Circuit Theory and Applications10.1002/cta.232345:11(1701-1741)Online publication date: Feb-2017
    • (2017)Technology ReviewFPGA‐based Implementation of Signal Processing Systems10.1002/9781119079231.ch4(70-93)Online publication date: 17-Feb-2017
    • (2016)Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversionApplied Soft Computing10.1016/j.asoc.2016.08.03549:C(447-461)Online publication date: 1-Dec-2016
    • (2015)Numerical Program Optimization for High-Level SynthesisProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689090(210-213)Online publication date: 22-Feb-2015

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