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Placement of repair circuits for in-field FPGA repair

Published: 11 February 2013 Publication History

Abstract

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This paper presents a method for repairing FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found in any logic block of the FPGA. This approach relies on logic placement to create "repair" circuits that avoid specific logic blocks. Three repair placement algorithms will be presented that generate a complete set of repair designs during the conventional placement process. The number of repairs needed to create a complete repair set depends heavily on the utilization of the FPGA resources. The three algorithms are tested against several benchmarks and with multiple area constraints for each benchmark. The best repair placement approach described in the paper generates a full set of repair circuits at a computation cost of 16X that of a conventional placer and with circuits of comparable quality.

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Cited By

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  • (2019)Third Party CAD Tools for FPGA Design—A Survey of the Current LandscapeIntelligent Information and Database Systems10.1007/978-3-030-17227-5_25(353-367)Online publication date: 29-Mar-2019
  • (2017)Vivado design interface: An export/import capability for Vivado FPGA designs2017 27th International Conference on Field Programmable Logic and Applications (FPL)10.23919/FPL.2017.8056809(1-7)Online publication date: Sep-2017
  • (2015)RapidSmith 2Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689085(66-69)Online publication date: 22-Feb-2015

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      cover image ACM Conferences
      FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
      February 2013
      294 pages
      ISBN:9781450318877
      DOI:10.1145/2435264
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 February 2013

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      Author Tags

      1. FPGA
      2. fault-tolerance
      3. placement
      4. repair
      5. simulated annealing

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      View all
      • (2019)Third Party CAD Tools for FPGA Design—A Survey of the Current LandscapeIntelligent Information and Database Systems10.1007/978-3-030-17227-5_25(353-367)Online publication date: 29-Mar-2019
      • (2017)Vivado design interface: An export/import capability for Vivado FPGA designs2017 27th International Conference on Field Programmable Logic and Applications (FPL)10.23919/FPL.2017.8056809(1-7)Online publication date: Sep-2017
      • (2015)RapidSmith 2Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689085(66-69)Online publication date: 22-Feb-2015

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