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Minimum energy operation for clustered island-style FPGAs

Published: 11 February 2013 Publication History

Abstract

Despite the advantages offered by field-programmable gate arrays (FPGAs) for low-power systems requiring flexible computing resources, applications with the lowest power budgets still favor microprocessors and application-specific integrated circuits (ASICs). In order for such systems to exploit FPGAs, an FPGA achieving minimum energy operation is needed. Minimum energy points have been found for ASICs and microprocessors to occur at operating voltages that are typically below the transistor threshold voltage. This paper presents two clustered island-style test chips capable of operating with a single supply voltage as low as 260 mV. This supply voltage represents the lowest voltage at which an FPGA has been successfully programmed. Test chip measurements show that the minimum energy point of both circuits is at or below this minimum operating voltage. Operation at 260 mV leads to a 40X power-delay product reduction vs. 1.5V operation. The results demonstrate a clear path forward for fabricating low voltage FPGAs that are fully compatible with existing tool flows.

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Cited By

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  • (2021)Static power model for CMOS and FPGA circuitsIET Computers & Digital Techniques10.1049/cdt2.1202115:4(263-278)Online publication date: 23-Mar-2021
  • (2020)Optimizing FPGA Logic Circuitry for Variable Voltage SuppliesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.296250128:4(890-903)Online publication date: Apr-2020
  • (2019)Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00011(1-8)Online publication date: Sep-2019
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      cover image ACM Conferences
      FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
      February 2013
      294 pages
      ISBN:9781450318877
      DOI:10.1145/2435264
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 February 2013

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      1. FPGA
      2. subthreshold

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      View all
      • (2021)Static power model for CMOS and FPGA circuitsIET Computers & Digital Techniques10.1049/cdt2.1202115:4(263-278)Online publication date: 23-Mar-2021
      • (2020)Optimizing FPGA Logic Circuitry for Variable Voltage SuppliesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.296250128:4(890-903)Online publication date: Apr-2020
      • (2019)Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00011(1-8)Online publication date: Sep-2019
      • (2014)Look-up Table Design for Deep Sub-threshold through Full-Supply Operation2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2014.80(259-266)Online publication date: May-2014

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