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A remote memory access infrastructure for global address space programming models in FPGAs

Published: 11 February 2013 Publication History

Abstract

We are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for FPGA and CPU components in a heterogeneous system. Our intent is to ease the integration of reconfigurable hardware into parallel programming models like Partitioned Global Address Space (PGAS). For this purpose, we introduce a remote memory access component based on Active Messages that implements the core API of the Berkeley GASNet communication library, and a simple controller that manages communication and synchronization for custom FPGA cores. We demonstrate how these components deliver a simple and easily configurable communication mechanism between distributed memories in a multi-FPGA system with processors as well as custom hardware nodes.

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Cited By

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  • (2022)Data Management Model to Program Irregular Compute Kernels on FPGA: Application to Heterogeneous Distributed SystemEuro-Par 2021: Parallel Processing Workshops10.1007/978-3-031-06156-1_8(91-103)Online publication date: 9-Jun-2022
  • (2020)A Service-Oriented Memory Architecture for FPGA Computing2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00025(91-97)Online publication date: Aug-2020
  • (2018)Enabling Efficient Job Dispatching in Accelerator-Extended Heterogeneous Systems with Unified Address Space2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/CAHPC.2018.8645945(180-188)Online publication date: Sep-2018
  • Show More Cited By

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cover image ACM Conferences
FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
February 2013
294 pages
ISBN:9781450318877
DOI:10.1145/2435264
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 February 2013

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Author Tags

  1. FPGA
  2. PGAs
  3. RDMA
  4. parallel programming models

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all
  • (2022)Data Management Model to Program Irregular Compute Kernels on FPGA: Application to Heterogeneous Distributed SystemEuro-Par 2021: Parallel Processing Workshops10.1007/978-3-031-06156-1_8(91-103)Online publication date: 9-Jun-2022
  • (2020)A Service-Oriented Memory Architecture for FPGA Computing2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00025(91-97)Online publication date: Aug-2020
  • (2018)Enabling Efficient Job Dispatching in Accelerator-Extended Heterogeneous Systems with Unified Address Space2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/CAHPC.2018.8645945(180-188)Online publication date: Sep-2018
  • (2017)HGum: Messaging framework for hardware accelerators2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2017.8279799(1-8)Online publication date: Dec-2017
  • (2015)Software-Driven Hardware DevelopmentProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689064(13-22)Online publication date: 22-Feb-2015
  • (2015)Heterogeneous Hardware Accelerators with Hybrid InterconnectProceedings of the 2015 International Conference on Advanced Computing and Applications (ACOMP)10.1109/ACOMP.2015.26(59-66)Online publication date: 23-Nov-2015
  • (2014)A Heterogeneous GASNet Implementation for FPGA-accelerated ComputingProceedings of the 8th International Conference on Partitioned Global Address Space Programming Models10.1145/2676870.2676885(1-9)Online publication date: 6-Oct-2014
  • (2014)Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication ProfilingProceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops10.1109/IPDPSW.2014.21(151-160)Online publication date: 19-May-2014

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