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FPGA bitstream compression and decompression using LZ and golomb coding (abstract only)

Published: 11 February 2013 Publication History

Abstract

In this paper we propose an optimized bitstream compression algorithm based on LZ and a novel architecture of decompressor, the proposed algorithm improves the Compression Ratio by fully utilizing the regularity of configuration bits of CLB (Configurable Logic Box) in FPGA and using the variable length Golomb coding method. The experimental results show that the Optimized method can improve the Compression Ratio of LZSS by 32.3% for bitstream with high regularity and 10.3% for bitstream with low regularity, and our approach shows a higher flexibility than the BMC+RLE arithmetic when compressing the bitstream with high regularity for various FPGA. Moreover, we design a two-buffer-window decompressor to download the compressed bitstreams. In order to increase the throughput of the proposed decompressor, we design a multi-stage data selector in it. The post-simulation of the decompressor shows that its throughput is up to 9280 Mbps under 65nm CMOS process. And that is 4352Mbps when verified on a Virtex-5 FPGA.

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Cited By

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  • (2015)An Architecture for Configuring an Effcient Scan Path for a Subset of ElementsProceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop10.1109/IPDPSW.2015.124(144-153)Online publication date: 25-May-2015

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cover image ACM Conferences
FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
February 2013
294 pages
ISBN:9781450318877
DOI:10.1145/2435264

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New York, NY, United States

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Published: 11 February 2013

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Author Tags

  1. FPGA bitstream
  2. LZ
  3. compression
  4. decompression
  5. golomb coding

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  • (2015)An Architecture for Configuring an Effcient Scan Path for a Subset of ElementsProceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop10.1109/IPDPSW.2015.124(144-153)Online publication date: 25-May-2015

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