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Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)

Published: 11 February 2013 Publication History

Abstract

When developing applications to run on FPGAs, we tend to expend great effort on crafting the custom hardware acceleration datapath---but blindly turn to the FPGA vendor tool/library to provide default solutions for on-chip interconnect and external interfaces. This often leads to ineffective communication- or memory-bound implementations since the design and tuning of the default general-purpose solutions necessarily makes design compromises for generality. This is counterproductive as the FPGA's flexible reconfigurability should afford us great opportunities for performance gain and cost reduction through extensive application-specific customization of the interconnect and interface IPs. This work presents a compiler that generates custom interconnect topology and connectivity with appropriately scaled capacity to support an application's exact communication requirements at a minimized cost. More specifically, the compiler analyzes an application developed for the CoRAM abstraction [1,2] for its connectivity and bandwidth requirements between the hardware processing kernels and external DRAM banks. The result is an extremely fine-tuned custom-topology soft-logic network-on-chip interconnect, which is enabled by the CONNECT NoC framework [3].
We perform an extensive evaluation that benchmarks two applications against the standard CoRAM implementation flow that relies on a fixed generically-tuned general-purpose soft-logic network-on-chip. Our RTL-driven evaluation shows a large opportunity for area reduction and improved efficiency (up by 48%) without any impact on application performance.

References

[1]
E. S. Chung, J. C. Hoe, and K. Mai. CoRAM: An in-fabric memory architecture for FPGA-based computing. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA'11, pages 97--106, New York, NY, USA, 2011.
[2]
E. S. Chung, M. K. Papamichael, G. Weisz, J. C. Hoe, and K. Mai. Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '12, pages 139--142, New York, NY, USA, 2012.
[3]
M. K. Papamichael and J. C. Hoe. CONNECT: Re-examining conventional wisdom for designing NOCS in the context of FPGAs. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '12, pages 37--46, New York, NY, USA, 2012.

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  1. Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)

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    cover image ACM Conferences
    FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
    February 2013
    294 pages
    ISBN:9781450318877
    DOI:10.1145/2435264

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    New York, NY, United States

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    Published: 11 February 2013

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    Author Tags

    1. data distribution
    2. memory systems
    3. network-on-chip

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