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Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only)

Published: 11 February 2013 Publication History

Abstract

Field programmable gate arrays (FPGA) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with FPGAs for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; FPGAs, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and FPGAs as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and FPGAs. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined FPGA implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

Cited By

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  • (2024)IoT Data Security by Combining Cryptography and Local Differential PrivacyInnovations in Cybersecurity and Data Science10.1007/978-981-97-5791-6_48(661-671)Online publication date: 13-Dec-2024
  • (2014)Design, implementation and security analysis of Hardware Trojan Threats in FPGA2014 IEEE International Conference on Communications (ICC)10.1109/ICC.2014.6883404(719-724)Online publication date: Jun-2014
  • (2013)High throughput implementations of cryptography algorithms on GPU and FPGA2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)10.1109/I2MTC.2013.6555510(723-727)Online publication date: May-2013

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  1. Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only)

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      cover image ACM Conferences
      FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
      February 2013
      294 pages
      ISBN:9781450318877
      DOI:10.1145/2435264

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 February 2013

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      Author Tags

      1. cryptography
      2. field programmable gate arrays
      3. graphics processing units
      4. parallel processing
      5. tiny encryption algorithm

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      Cited By

      View all
      • (2024)IoT Data Security by Combining Cryptography and Local Differential PrivacyInnovations in Cybersecurity and Data Science10.1007/978-981-97-5791-6_48(661-671)Online publication date: 13-Dec-2024
      • (2014)Design, implementation and security analysis of Hardware Trojan Threats in FPGA2014 IEEE International Conference on Communications (ICC)10.1109/ICC.2014.6883404(719-724)Online publication date: Jun-2014
      • (2013)High throughput implementations of cryptography algorithms on GPU and FPGA2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)10.1109/I2MTC.2013.6555510(723-727)Online publication date: May-2013

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