ABSTRACT
The impact of process variation (PV) in deep submicron CMOS technologies has raised major concerns for energy optimization efforts in FPGAs. We have developed a post-silicon leakage energy optimization scheme that raises the threshold voltage (by way of negative bias temperature instability (NBTI) aging) of the components that are either unused or not on the critical timing paths, thereby reducing the total leakage energy consumption. In order to obtain the input vectors for aging only the targeted transistors, we map the problem of minimizing leakage energy under timing constraints to an instance of the satisfiability (SAT) problem. We implemented low power designs targeting Xilinx Spartan6 FPGAs and analyzed the potential leakage power savings over a set of ITC99 and Opencores benchmarks. The analysis of the experimental results shows a substantial amount of potential leakage energy reduction with very small performance degradation.
- D. Markovic, C. Wang, L. Alarcon, T. Liu, J. Rabaey, Ultralow-Power Design in Near-Threshold Region, Proceedings of the IEEE, Vol. 98, No. 2, pp. 237--252, 2010.Google ScholarCross Ref
- S. Chakravarthi , A. Krishnan, V. Reddy, C. Machala, S. Krishnan, A Comprehensive Framework for Predictive Modeling of Negative Bias Temperature Instability, IRPS 2004, pp. 273--282.Google Scholar
- K. Bernstein , D. Frank, A. Gattiker, W. Haensch, B. Ji, S. Nassif, E. Nowak, D. Pearson, N. Rohrer, High-performance CMOS Variability in the 65-nm Regime and Beyond, IBM Journal of Research and Development, Vol. 50, No. 4/5, pp. 433--449, 2006. Google ScholarDigital Library
- X. Li, F. Wang, T. La, Z. Ling, FPGA as Process Monitor - An Effective Method to Characterize Poly Gate CD Variation and Its Impact on Product Performance and Yield, IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 3, pp. 267--272, 2004.Google ScholarCross Ref
- S. Velusamy, W. Huang, J. Lach, M. Stan, K. Skadron, Monitoring Temperature in FPGA based SoCs, ICCD 2005, pp. 634--637. Google ScholarDigital Library
- F. Bruguier, P. Benoit, P. Maurine, L. Torres, A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis, FPL 2011, pp. 20--23. Google ScholarDigital Library
- A. Kumar, M. Anis, FPGA Design for Timing Yield Under Process Variations, IEEE Transactions on VLSI Systems, Vol. 18, No. 3, pp. 423--435, 2010. Google ScholarDigital Library
- R. Rubin, A. DeHon, Choose-your-own-adventure Routing: Lightweight Load-time Defect Avoidance, FPGA 2009, pp. 23--32. Google ScholarDigital Library
- A. Nowroz, S. Reda, Thermal and Power Characterization of Field-programmable Gate Arrays, FPGA 2011, pp. 111--114. Google ScholarDigital Library
- L. Cheng, J. Xiong, L. He, M. Hutton, FPGA Performance Optimization via Chipwise Placement Considering Process Variations, FPL 2006, pp. 1--6.Google Scholar
- Y. Matsumoto, M. Hioki, T. Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa, H. Koike, Performance and Yield enhancement of FPGAs with within-die Variation Using Multiple Configurations, FPGA 2007, pp.169--177. Google ScholarDigital Library
- S. Sivaswamy, K. Bazargan, Variation-aware Routing for FPGAs, FPGA 2007, pp. 71--79. Google ScholarDigital Library
- A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. Irwin, T. Tuan, A Dual Vdd Low Power FPGA Architecture, FPGA 2004, pp. 51--58.Google Scholar
- F. Li, Y .Lin, J. Cong, Low Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics. FPGA 2004, pp. 42--50. Google ScholarDigital Library
- C. Chow, L. Tsui, P. Leong, W. Luk, S. Wilton, Dynamic Voltage Scaling for Commercial, FPT 2005, pp. 173--180.Google Scholar
- B. Kheradmand-Boroujeni, C. Piguet, Y. Leblebici, AVGS-Mux Style: A Novel Technology and Device Independent Technique for Reducing Power and Compensating Process Variations in FPGA Fabrics, DATE 2010, pp. 339--344. Google ScholarDigital Library
- J. Lamoureux, G. Lemieux, S. Wilton, GlitchLess: An Active Glitch Minimization Technique for FPGAs, FPGA 2007, pp. 156--165. Google ScholarDigital Library
- S. Wei, S. Meguerdichian, M. Potkonjak, Gate-level Characterization: Foundations and Hardware Security Applications, DAC 2010, pp. 222--227. Google ScholarDigital Library
- S.Srinivasan, A. Gayasen, N. Vijaykrishnan, T. Tuan, Leakage Control in FPGA Routing Fabric, ASP-DAC 2005, pp. 661--664. Google ScholarDigital Library
- Y. Alkabani, T. Massey, F. Koushanfar, M. Potkonjak, Input Vector Control for Post-silicon Leakage Current Minimization in the Presence of Manufacturing Variability, DAC 2008, pp. 606--609. Google ScholarDigital Library
- A. Srivastava, D. Sylvester, D. Blaauw, Statistical Optimization of Leakage Power Considering Process Variations Using Dual-Vth and Sizing, DAC 2004, pp. 773--778. Google ScholarDigital Library
- W. Wang , S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S. Vrudhula, Y. Cao, The Impact of NBTI on the Performance of Combinational and Sequential Circuits, DAC 2007, pp. 364--369. Google ScholarDigital Library
- ITC99 Benchmark Home Page, http://www.cerc.utexas.edu/itc99-benchmarks/bench.htmlGoogle Scholar
- Opencores, http://opencores.org/Google Scholar
- B. Cheng, S. Roya, A. Browna, C. Millara, A. Asenov, Evaluation of Statistical Technology Generation LSTP MOSFETs, Solid-State Electronics, Vol. 53, pp. 767--772, 2009.Google ScholarCross Ref
- S. Roy, A. Asenov, Where Do the Dopants Go? Science, Vol. 309, No. 5733, pp. 388--390, 2005.Google ScholarCross Ref
- A. Asenov, Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 um MOSFET's: A 3-D Atomistic Simulation Study, IEEE Transactions on Electron Devices, Vol. 45, No. 12, pp. 2505--2513, 1998.Google ScholarCross Ref
- A. Rahman, V. Polavarapuv, Evaluation of Low-leakage Design Techniques for Field Programmable Gate Arrays, FPGA 2004, pp. 23--30. Google ScholarDigital Library
- B. Cline, K. Chopra, D. Blaauw, Y. Cao, Analysis and Modeling of CD Variation for Statistical Static Timing, ICCAD 2006, pp. 60--66. Google ScholarDigital Library
- Y. Kim, V. Narayanan, C. Cabral, V. Paruchuri, B. Doris, J. Stathis, A. Callegari, M. Chudzik, A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates, VLSI 2006, pp. 23--25.Google Scholar
Index Terms
- Low power FPGA design using post-silicon device aging (abstract only)
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