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Circuit optimizations to minimize energy in the global interconnect of a low-power--FPGA (abstract only)

Published: 11 February 2013 Publication History

Abstract

We compare circuit and architecture choices in the global interconnect of an FPGA in order to find the minimum energy design for low voltage operation. We look at switch box topology, number of repeaters, receiver circuit topology, and dynamic voltage selection, all with the intent of minimizing energy consumption. The results show that using a pass gate switchbox topology with repeaters in the interconnect and a custom receiver lowers delay by up to 63% and energy by up to 87% from the standard FPGA circuit choices. This work also identifies the optimal VDD choices to maximize performance under energy constraints or vice versa.

References

[1]
Calhoun, B. H., J. Ryan, S. Khanna, M. Putic, and J. Lach, "Flexible Circuits and Architectures for Ultra Low Power", Proceedings of the IEEE, vol. 98, pp. 267--282, 2010.
[2]
Ryan, J. F., and B. H. Calhoun, "A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS", CICC, 2010.
[3]
https://sites.google.com/site/xiaoleicustc/research/mcnc
[4]
Krishnan, R.; de Gyvez, J.P., "Low energy switch block for FPGAs," VLSI Design, pp. 209- 214, 2004
[5]
Anderson, J.H.; Najm, F.N., "A novel low-power FPGA routing switch," Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, pp. 719--722, 2004
[6]
Vaughn Betz and Jonathan Rose, "FPGA routing architecture: segmentation and buffering to optimize speed and density," Field programmable gate arrays (FPGA '99) pp. 59--68, 1999.
[7]
Mukherjee, R.; Memik, S.O., "Evaluation of dual VDD fabrics for low power FPGAs," ASP-Design Automation Conference, 2005

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  1. Circuit optimizations to minimize energy in the global interconnect of a low-power--FPGA (abstract only)

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    cover image ACM Conferences
    FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
    February 2013
    294 pages
    ISBN:9781450318877
    DOI:10.1145/2435264

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    Association for Computing Machinery

    New York, NY, United States

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    Published: 11 February 2013

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    Author Tags

    1. FPGA
    2. circuit optimization
    3. dual-vdd implementation
    4. dynamic voltage scaling
    5. global interconnect
    6. sub-threshold FPGA

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