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Rectification of advanced microprocessors without changing routing on FPGAs (abstract only)

Published: 11 February 2013 Publication History

Abstract

We propose a method for rectification of bugs in microprocessors that are implemented on FPGAs, by only changing the configuration of LUTs, without any modification to the routing. Therefore, correcting the bugs does not require resynthesis, which can be very long for complex microprocessors due to possible timing closure problems. As the structure of the circuit is preserved, correcting the bugs does not affect the timings of the circuit. In design phase, we may add additional LUTs to the original circuit, so that we can use them in the correction phase. After a bug is found, we perform the following two tasks. Fist, we find the candidate control signals as well as the required change to correct their behavior. This is done by using symbolic simulation and equivalency checking between the formal specification and the erroneous formal model of the processor. Then, we try to map the corrected functionality into the existing LUT structure. This is done by a novel method that formulates the problem as a QBF (Quantified Boolean Formula) problem, and solves it by repeatedly applying normal SAT solvers instead of QBF solvers under a CEGAR (Counter Example Guided Abstraction Refinement) paradigm. We show effectiveness of our method by correcting bugs in two complex out-of-order superscalar processors with two different timing error recovery mechanisms.

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  • (2018)An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00076(403-4037)Online publication date: Aug-2018

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  1. Rectification of advanced microprocessors without changing routing on FPGAs (abstract only)

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        cover image ACM Conferences
        FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
        February 2013
        294 pages
        ISBN:9781450318877
        DOI:10.1145/2435264

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        Association for Computing Machinery

        New York, NY, United States

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        Published: 11 February 2013

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        Author Tags

        1. CEGAR
        2. FPGA
        3. QBF
        4. design error diagnosis
        5. design error rectification
        6. formal verification
        7. microprocessors

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        • (2018)An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00076(403-4037)Online publication date: Aug-2018

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