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Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)

Published: 11 February 2013 Publication History

Abstract

Despite their many advantages, FPGAs are still inefficient. This inefficiency is mainly due to programmable routing networks; however, FPGA logic blocks also have their share of contribution. From the performance perspective, fewer hops in the routing network translates to a shorter critical path; and that requires large logic blocks capable of covering big portions of circuits. Recent work has shown that And-Inverter Cones (AICs) can considerably reduce the number of logic block levels compared to Look-Up Tables (LUTs). The best performance is achieved when both AICs and LUTs are used, but the AIC implementation requires radical changes in the FPGAs architecture. In this paper, we use AICs as shadow logic for LUTs in LUT-clusters, which requires minimal architectural changes while exploiting the benefits of both AICs and LUTs. The basic idea is to reuse the input crossbar of LUT-clusters for the shadow AICs while combining both LUTs and AICs in the same cluster. We also propose changes in the AIC architecture to enhance mapping on AICs. Our experimental results indicate that the new cluster architecture can reduce the average circuit delay by 12% with respect to standard FPGA clusters. However, this performance gain comes at a price of 43% area overhead in terms of number of logic clusters. Our results show that for a modest 6% increase in area, FPGA manufacturers can move towards next-generation FPGA logic elements. This transition would provide faster design options without major architectural changes.

Cited By

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  • (2021)FPGA Architecture: Principles and ProgressionIEEE Circuits and Systems Magazine10.1109/MCAS.2021.307160721:2(4-29)Online publication date: Oct-2022
  • (2017)A Hybrid Logic Block Architecture in FPGA for Holistic EfficiencyIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.255155564:1(71-75)Online publication date: Jan-2017
  • (2014)Revisiting and-inverter conesProceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays10.1145/2554688.2554791(45-54)Online publication date: 26-Feb-2014
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  1. Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)

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      cover image ACM Conferences
      FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
      February 2013
      294 pages
      ISBN:9781450318877
      DOI:10.1145/2435264

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      Association for Computing Machinery

      New York, NY, United States

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      Published: 11 February 2013

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      Author Tags

      1. FPGA logic block
      2. and-inverter cone
      3. shadow logic
      4. technology mapping

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      Cited By

      View all
      • (2021)FPGA Architecture: Principles and ProgressionIEEE Circuits and Systems Magazine10.1109/MCAS.2021.307160721:2(4-29)Online publication date: Oct-2022
      • (2017)A Hybrid Logic Block Architecture in FPGA for Holistic EfficiencyIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.255155564:1(71-75)Online publication date: Jan-2017
      • (2014)Revisiting and-inverter conesProceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays10.1145/2554688.2554791(45-54)Online publication date: 26-Feb-2014
      • (2014)Towards dark silicon era in FPGAs using complementary hard logic design2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927504(1-6)Online publication date: Sep-2014

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