research-article

Improving dynamic binary optimization through early-exit guided code region formation

Authors:

Ding-Yong Hong,

Chien-Min WangAuthors Info & Claims

VEE '13: Proceedings of the 9th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments

Pages 23 - 32

https://doi.org/10.1145/2451512.2451519

Published: 16 March 2013 Publication History

Abstract

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces.

In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multi-threaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NET-variant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of up to 72% (27% on average), and to 49% (23% on average) for IA32 and ARM, respectively.

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Cited By

Jiang JDong RZhou ZSong CWang WYew PZhang W(2020)More with Less – Deriving More Translation Rules with Less Training Data for DBTs Using Parameterization2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00043(415-426)Online publication date: Oct-2020
https://doi.org/10.1109/MICRO50266.2020.00043
Song CWang WYew PZhai AZhang WDan TDahlia M(2019)Unleashing the power of learningProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358815(77-89)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.5555/3358807.3358815
Wang WWu JGong XLi TYew P(2018)Improving Dynamically-Generated Code Performance on Dynamic Binary TranslatorsACM SIGPLAN Notices10.1145/3296975.318641353:3(17-30)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3296975.3186413
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Index Terms

Improving dynamic binary optimization through early-exit guided code region formation
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Incremental compilers
      2. Runtime environments

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Improving dynamic binary optimization through early-exit guided code region formation
VEE '13

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of ...

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cover image ACM Conferences

VEE '13: Proceedings of the 9th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments

March 2013

210 pages

ISBN:9781450312660

DOI:10.1145/2451512

General Chair:
Steve Muir
VMware, USA
,
Program Chairs:
Gernot Heiser
NICTA and University of New South Wales, Australia
,
Steve Blackburn
Australian National University, Australia

ACM SIGPLAN Notices Volume 48, Issue 7
VEE '13
July 2013
194 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/2517326
Issue’s Table of Contents

Copyright © 2013 ACM.

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Published: 16 March 2013

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VEE '13: ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

March 16 - 17, 2013

Texas, Houston, USA

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Cited By

Jiang JDong RZhou ZSong CWang WYew PZhang W(2020)More with Less – Deriving More Translation Rules with Less Training Data for DBTs Using Parameterization2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00043(415-426)Online publication date: Oct-2020
https://doi.org/10.1109/MICRO50266.2020.00043
Song CWang WYew PZhai AZhang WDan TDahlia M(2019)Unleashing the power of learningProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358815(77-89)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.5555/3358807.3358815
Wang WWu JGong XLi TYew P(2018)Improving Dynamically-Generated Code Performance on Dynamic Binary TranslatorsACM SIGPLAN Notices10.1145/3296975.318641353:3(17-30)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3296975.3186413
Wang WMcCamant SZhai AYew P(2018)Enhancing Cross-ISA DBT Through Automatically Learned Translation RulesACM SIGPLAN Notices10.1145/3296957.317716053:2(84-97)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3177160
Hong DWu JLiu YFu SHsu W(2018)Processor-Tracing Guided Region Formation in Dynamic Binary TranslationACM Transactions on Architecture and Code Optimization10.1145/328166415:4(1-25)Online publication date: 16-Nov-2018
https://dl.acm.org/doi/10.1145/3281664
Wang WWu JGong XLi TYew P(2018)Improving Dynamically-Generated Code Performance on Dynamic Binary TranslatorsProceedings of the 14th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments10.1145/3186411.3186413(17-30)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3186411.3186413
Wang WMcCamant SZhai AYew PShen XTuck JBianchini RSarkar V(2018)Enhancing Cross-ISA DBT Through Automatically Learned Translation RulesProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3177160(84-97)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3177160
Hong DHsu CChou CHsu WLiu PWu J(2015)Optimizing Control Transfer and Memory Virtualization in Full System EmulatorsACM Transactions on Architecture and Code Optimization10.1145/283702712:4(1-24)Online publication date: 8-Dec-2015
https://dl.acm.org/doi/10.1145/2837027
Spink TWagstaff HFranke BTopham N(2014)Efficient code generation in a region-based dynamic binary translatorACM SIGPLAN Notices10.1145/2666357.259781049:5(3-12)Online publication date: 12-Jun-2014
https://dl.acm.org/doi/10.1145/2666357.2597810
Jia NYang CHe YCheng XDekel EBurns RFriedman R(2014)SPTUProceedings of International Conference on Systems and Storage10.1145/2611354.2611368(1-12)Online publication date: 30-Jun-2014
https://dl.acm.org/doi/10.1145/2611354.2611368
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