research-article

Benchmarking for research in power delivery networks of three-dimensional integrated circuits

Authors:

Yung-Tai Chang,

Liang-Chia Cheng,

Ding-Ming Kwai,

Yiyu ShiAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 17 - 24

https://doi.org/10.1145/2451916.2451922

Published: 24 March 2013 Publication History

Abstract

Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in academia to model, design or optimize the power delivery networks (PDNs) in 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none is available in the context of 3D. As a consequence, most existing literature resorts to ad-hoc designs by artificially stacking 2D PDNs for experiments, rendering the results less convincing. In this paper, we put forward a set of ten PDN benchmarks that are extracted from industrial 3D designs. These designs are carefully selected such that they cover a wide range of functionality, size, TSV number, tier number and packaging style. We hope that the released benchmarks can facilitate and promote research in 3D PDNs.

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Cited By

Shen SLiu ZYu W(2024)SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528743(1-7)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528743
Chhabria VKunal KZabihi MSapatnekar S(2021)BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643566(1-8)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643566
Samal SSamadi KKamal PDu YLim S(2019)Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261637736:6(992-1003)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2016.2616377
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Index Terms

Benchmarking for research in power delivery networks of three-dimensional integrated circuits
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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cover image ACM Conferences

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

Publication History

Published: 24 March 2013

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ISPD'13

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ISPD'13: International Symposium on Physical Design

March 24 - 27, 2013

Nevada, Stateline, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Shen SLiu ZYu W(2024)SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528743(1-7)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528743
Chhabria VKunal KZabihi MSapatnekar S(2021)BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643566(1-8)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643566
Samal SSamadi KKamal PDu YLim S(2019)Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261637736:6(992-1003)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2016.2616377
Samal SLim S(2019)Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D-ICsHandbook of 3D Integration10.1002/9783527697052.ch6(115-140)Online publication date: 8-Feb-2019
https://doi.org/10.1002/9783527697052.ch6
Wang YYao STao SChen XMa YShi YYang H(2015)HS3-DPG: Hierarchical Simulation for 3-D P/G NetworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.235858223:10(2307-2311)Online publication date: Oct-2015
https://doi.org/10.1109/TVLSI.2014.2358582
Xuan Wang Jiang Xu Wei Zhang Xiaowen Wu Yaoyao Ye Zhehui Wang Nikdast MZhe Wang (2015)Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.230695923:2(266-279)Online publication date: Feb-2015
https://doi.org/10.1109/TVLSI.2014.2306959
Samal SSamadi KKamal PDu YLim SChang Y(2014)Full chip impact study of power delivery network designs in monolithic 3D ICsProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691477(565-572)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691477
Shi YChen HFettweis GNebel W(2014)MemcomputingProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616997(1-3)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616997
Yao SChen XWang YMa YXie YYang H(2014)Efficient region-aware P/G TSV planning for 3D ICsFifteenth International Symposium on Quality Electronic Design10.1109/ISQED.2014.6783321(171-178)Online publication date: Mar-2014
https://doi.org/10.1109/ISQED.2014.6783321
Samal SSamadi KKamal PDu YLim S(2014)Full chip impact study of power delivery network designs in monolithic 3D ICs2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001406(565-572)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001406
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