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PushPull: short path padding for timing error resilient circuits

Published: 24 March 2013 Publication History

Abstract

Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short path padding (hold time fixing) problem in resilient circuits is severer than conventional IC design. Therefore, in this paper, we focus on the short path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we propose coarse-grained and fine-grained padding allocation methods to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error resilient circuits.

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Cited By

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  • (2015)An Improved Methodology for Resilient Design ImplementationACM Transactions on Design Automation of Electronic Systems10.1145/274946220:4(1-26)Online publication date: 28-Sep-2015
  • (2014)A new methodology for reduced cost of resilienceProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591600(157-162)Online publication date: 20-May-2014
  • (2014)PushPullIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.230468133:4(558-570)Online publication date: 1-Apr-2014

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      cover image ACM Conferences
      ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design
      March 2013
      194 pages
      ISBN:9781450319546
      DOI:10.1145/2451916
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      Publication History

      Published: 24 March 2013

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      Author Tags

      1. delay padding
      2. dynamic variations
      3. engineering change order
      4. hold time fixing
      5. resilient circuits
      6. timing analysis

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      March 24 - 27, 2013
      Nevada, Stateline, USA

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      Cited By

      View all
      • (2015)An Improved Methodology for Resilient Design ImplementationACM Transactions on Design Automation of Electronic Systems10.1145/274946220:4(1-26)Online publication date: 28-Sep-2015
      • (2014)A new methodology for reduced cost of resilienceProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591600(157-162)Online publication date: 20-May-2014
      • (2014)PushPullIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.230468133:4(558-570)Online publication date: 1-Apr-2014

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