research-article

Delay-driven layer assignment in global routing under multi-tier interconnect structure

Authors:

Satoshi GotoAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 101 - 107

https://doi.org/10.1145/2451916.2451942

Published: 24 March 2013 Publication History

Abstract

A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the interconnect delay. However, such layer dependent characteristics have been ignored by most of the state-of-the-art academic layer assignment methods. To remedy this deficiency, this work studies a more effective layer assignment problem under such multi-tier interconnect structure, which arises during 3D global routing and focuses on minimizing both delays and via count. This work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count. The experimental results on ICCAD09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count, compared with the state-of-the-art via count minimization layer assignment method NVM.

References

[1]

J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of IEEE, vol. 89, pp. 505--528, April 2001.

[2]

J. A. Davis and J. D. Meindl, Interconnect Technology and Design for Gigascale Integration, Kluwer Academic Publishers, 2003.

Digital Library

[3]

Z. Li, C. J. Alpert, S.Hu, T. Muhmud, S. T. Quay, and P. G. Vilarubia, "Fast interconnect synthesis with layer assignment," Proceedings of International Symposium on Physical Design, pp. 71--77, 2008.

Digital Library

[4]

C. J. Alpert, C. Chu, and P. G. Villarrubia, "The coming age of physical design," Proceedings of International Conference on Computer-Aided Design, pp. 246--249, 2007.

Digital Library

[5]

M. D. Moffitt, "Global routing revisited," Proceedings of International Conference on Computer-Aided Design, pp. 805--808, 2009. http://web.eecs.umich.edu/~mmoffitt/iccad2009.alternate.html

Digital Library

[6]

ISPD 2007 Global Routing Contest. {Online}. Available: http://archive.sigda.org/ispd2007/contest.html

[7]

ISPD 2008 Global Routing Contest. {Online}. Available: http://archive.sigda.org/ispd2008/contests/ispd08rc.html

[8]

M. Cho, K. Lu, K. Yuan, and D. Z. Pan, "BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router," Proceedings of International Conference on Computer-Aided Design, pp. 503--508, 2007.

Digital Library

[9]

J. A. Roy and I. L. Markov, "High-performance routing at the nanometer scale," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6), pp. 1066--1077, 2008.

Digital Library

[10]

T.-H. Lee and T.-C. Wang, "Congestion-constrained layer assignment for via minimization in global routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(9), pp. 1643- 1656, 2008.

Digital Library

[11]

K.-R. Dai, W.-H. Liu, and Y.-L. Li, "Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing," Proceedings of Asia and South Pacific Design Automation Conference, pp. 570--575, 2009.

Digital Library

[12]

Y. Xu, Y. Zhang and C. Chu, "FastRoute 4.0: global router with efficient via minimization," Proceedings of Asia and South Pacific Design Automation Conference, pp. 576--581, 2009.

Digital Library

[13]

C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, "Multi-layer global routing considering via and wire capacities," Proceedings of International Conference on Computer-Aided Design, pp. 350--355, 2008.

Digital Library

[14]

T.-H. Lee and T.-C. Wang, "Robust layer assignment for via optimization in multi-layer global routing," Proceedings of International Symposium on Physical Design, pp. 159--166, 2009.

Digital Library

[15]

W.-H. Liu and Y.-L. Li, "Negotiation-based layer assignment for via count and via overflow minimization," Proceedings of Asia and South Pacific Design Automation Conference, pp. 539--544, 2011.

Digital Library

[16]

T.-H. Lee and T.-C. Wang, "Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing," Proceedings of International Conference on Computer-Aided Design, pp. 312--318, 2010.

Digital Library

[17]

W.-H. Liu, Y.-L. Li, "Optimizing the antenna area and separators in layer assignment of multi-layer global routing," Proceedings of International Symposium on Physical Design, pp. 137--144, 2012.

Digital Library

[18]

S. Hu, Z. Li, and C. J. Alpert, "A polynomial time approximation scheme for timing constrained minimum cost layer assignment," Proceedings of International Conference on Computer-Aided Design, pp. 112--115, 2008.

Digital Library

[19]

Y.-J. Chang, T.-H. Lee, and T.-C. Wang, "GLADE: a modern global router considering layer directives," Proceedings of International Conference on Computer-Aided Design, pp. 319--323, 2010.

Digital Library

[20]

T.-H. Lee, Y.-J. Chang, and T.-C. Wang, "An enhanced global router with consideration of general layer directives," Proceedings of International Symposium on Physical Design, pp. 53--60, 2011.

Digital Library

[21]

M. J. Ciesielski, "Layer assignment for VLSI interconnect delay minimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(6), pp. 702--707, 1989.

Digital Library

[22]

C.C. Chang and J. Cong, "An efficient approach to multilayer layer assignment with applications to via minimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(5), pp. 608--620, 1999.

Digital Library

[23]

P. Saxena and C. L. Liu, "Optimization of the maximum delay of global interconnects during layer assignment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(4), pp. 503--515, 2001.

Digital Library

[24]

D. Wu, J. Hu, R. Mahapatra, "Coupling aware timing optimization and antenna avoidance in layer assignment," Proc. International Symposium on Physical Design, 2005.

Digital Library

[25]

W.C. Elmore. "The transient response of damped linear networks with particular regard of wideband amplifiers," J. Appl. Phys., 19(1):55--63, Jan. 1948.

[26]

L. McMurchie and C. Ebeling, "Pathfinder: a negotiation-based performance- driven router for FPGAs," Proc. ACM Symposium on FPGAs, pp. 111--117, 1995.

Digital Library

[27]

Y.-J. Chang, Y.-T. Lee, and T.-C. Wang, "NTHU-Route 2.0: a fast and stable global router," Proceedings of International Conference on Computer-Aided Design, pp. 338--343, 2008.

Digital Library

[28]

Nangate 45nm open cell library, http://www.nangate.com, 2008.

Cited By

Yu YLi ZChen JHuang XLiu GXu N(2024)Multi-Strategy Bus Deviation-Driven Layer Assignment Algorithm2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617851(456-461)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617851
Lu RZhang WJiang LLiu G(2023)Slew-Driven Layer Assignment for Advanced Non-default-rule WiresWeb Information Systems and Applications10.1007/978-981-99-6222-8_45(539-550)Online publication date: 9-Sep-2023
https://doi.org/10.1007/978-981-99-6222-8_45
Jiang LLi ZBao CLiu GHuang XLiu WWang T(2022)LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939586(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939586
Show More Cited By

Index Terms

Delay-driven layer assignment in global routing under multi-tier interconnect structure
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

Robust layer assignment for via optimization in multi-layer global routing
ISPD '09: Proceedings of the 2009 international symposium on Physical design

In this paper, we study a layer assignment problem which arises during multi-layer global routing. Our layer assignment problem takes the total wire overflow and the maximum wire overflow of a given 2D global routing solution to form the wire congestion ...
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing

In this paper, we study the problem of layer assignment for via minimization, which arises during multilayer global routing. In addressing this problem, we take the total overflow and the maximum overflow as the congestion constraints from a given one-...
Optimizing the antenna area and separators in layer assignment of multi-layer global routing
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

Traditional solutions to antenna effect, such as jumper insertion and diode insertion peformed at post-route stage may produce extra vias and degrade circuit performance. The work in [1] suggests combining layer assignment, jumper insertion and diode ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 March 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISPD'13

Sponsor:

SIGDA

ISPD'13: International Symposium on Physical Design

March 24 - 27, 2013

Nevada, Stateline, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
255
Total Downloads

Downloads (Last 12 months)13
Downloads (Last 6 weeks)0

Reflects downloads up to 27 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Yu YLi ZChen JHuang XLiu GXu N(2024)Multi-Strategy Bus Deviation-Driven Layer Assignment Algorithm2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617851(456-461)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617851
Lu RZhang WJiang LLiu G(2023)Slew-Driven Layer Assignment for Advanced Non-default-rule WiresWeb Information Systems and Applications10.1007/978-981-99-6222-8_45(539-550)Online publication date: 9-Sep-2023
https://doi.org/10.1007/978-981-99-6222-8_45
Jiang LLi ZBao CLiu GHuang XLiu WWang T(2022)LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939586(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939586
Liu GZhang XGuo WHuang XLiu WChao KWang T(2022)Timing-Aware Layer Assignment for Advanced Process Technologies Considering via PillarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310029641:6(1957-1970)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3100296
Zhang XZhuang ZLiu GHuang XLiu WGuo WWang T(2020)MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116269(586-591)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116269
Tang HLiu GChen XXiong N(2020)A Survey on Steiner Tree Construction and Global Routing for VLSI DesignIEEE Access10.1109/ACCESS.2020.29861388(68593-68622)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2986138
Gandhi UBustany ISwartz WBehjat L(2019)A Reinforcement Learning-Based Framework for Solving Physical Design Routing Problem in the Absence of Large Test Sets2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD48534.2019.9142109(1-6)Online publication date: Sep-2019
https://doi.org/10.1109/MLCAD48534.2019.9142109
Held SMuller DRotter DScheifele RTraub VVygen J(2018)Global Routing With Timing ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269796437:2(406-419)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2697964
Liu DYu BChowdhury SPan D(2018)TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew ViolationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265222137:1(231-244)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2652221
Liu DYu BChowdhury SPan D(2017)Incremental Layer Assignment for Timing OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/308372722:4(1-25)Online publication date: 13-Jun-2017
https://dl.acm.org/doi/10.1145/3083727
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten