research-article

Network flow based datapath bit slicing

Authors:

Matthew Ziegler,

Ruchir PuriAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 139 - 146

https://doi.org/10.1145/2451916.2451954

Published: 24 March 2013 Publication History

Abstract

In deep sub-micro designs, more functions are integrated into one chip, and datapath has become a critical part of the design. Typical datapath consists an array of bit slices. The inherent high degree regularity of datapaths is especially attractive to the placement and routing to achieve regular layout with high density and high performance. However, the current design methodology may generate inferior datapath designs because the datapath regularity cannot be well understood by the traditional design tools. In previous works, several techniques are proposed to preserve/re-identify datapath structures. However, they either restrict the datapath optimization or have little tolerance on bit slice difference.

In this work, we present a novel approach to re-identify datapath bit slices. Contrary to the previous template-based approach, we convert the bit slicing problem to the bit matching problem. Then a min-cost max-flow based algorithm is proposed to identify the main-frame of bit slices so that the datapath bit matching is achieved. An efficient two way search approach is developed to derive the full bit slices based on the bit matching results. We further improve the bit slicing solution with an iterative method. The experimental results demonstrate the effectiveness and efficiency of our approach.

References

[1]

Synopsys Module Compiler User Manual.

[2]

R. K. Ahuja, A. V. Goldberg, J. B. Orlin, and R. E. Targan, Finding minimum-cost flows by double scaling, Mathematical programming 53, pp. 243--266, 1992.

[3]

R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows, Prentice Hall, 1993.

[4]

S. R. Arikati and R. Varadarajan, A Signature based Approach to Regularity Extraction, in Proc. Intl. Conf. on Computer Aided Design, 1997.

Digital Library

[5]

T. Chan, A. Chowdhary, B. Krishna, A. Levin, G. Meeker, and N. Sehgal, Challenges of CAD Development of Datapath Design, Intel Technology Journal Q1, 1999.

[6]

S. Chou, M-K Hsu, Y-W Chang, Structure-aware placement for datapath-intensive circuit designs, in Proc. DAC, 2012.

Digital Library

[7]

A. Chowdhary, and R. Gupta, A Methodology for Synthesis of Data Path Circuits, IEEE Design and Test of Computers, 2002.

Digital Library

[8]

A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, and R. Gupta, A General Approach for Regularity Extraction in Datapath Circuits, in Proc. Intl. Conf. on Computer-Aided Design, Nov, 1998.

Digital Library

[9]

M.R. Corazao, M.A. Khalaf, L.M. Guerra, M. Potkonjak, and J.M. Rabaey, Performance optimization using template mapping for datapath-intensive high-level synthesis, In IEEE Transactions on CAD, pp. 877--887, Aug, 1996.

Digital Library

[10]

T. Cormen, C. Leiserson, R. Rivest, and C. Stein, Introduction to Algorithms, the MIT press.

[11]

S. Das, and S.P. Khatri, A Regularity-Driven Fast Gridless Detailed Router for High Frequency Datapath Designs, ISPD, 2001.

Digital Library

[12]

S. Hassoun, and C. McCreary, Regularity Extraction Via Clan-Based Structural Circuit Decomposition, in Proc. Intl. Conf. on Computer-Aided Design, Nov, 1999.

Digital Library

[13]

T. Kutzschebauch, Efficient Logic Optimization Using Regularity Extraction, in Proc. Intl. Conf. on Computer Design, 2000.

Digital Library

[14]

T. Kutzschebauch, and L. Stok, Regularity Driven Logic Synthesis, in Proc. Intl. Conf. on Computer-Aided Design, 2000.

Digital Library

[15]

D. S. Rao and F. J. Kurdahi, Partitioning by Regularity Extraction, in Proc. Design Automation Conf., 1992.

Digital Library

[16]

D. S. Rao and F. J. Kurdahi, On Clustering for Maximal Regularity Extraction, IEEE Trans. on Computer Aided Design, vol 12, 1993.

[17]

A. P. E. Rosiello, F. Ferrandi, D. Pandini, and D. Sciuto, A Hash-based Approach for Functional Regularity Extraction during Logic Synthesis, IEEE Computer Society Annual Symposium on VLSI, 2007.

Digital Library

[18]

S. I. Ward, M. Kim, N. Viswanathan, Z. Li, C. Alpert, E. E. Swartzlander, Jr., D. Z. Pan, Keep it Straight: Teaching Placement how to Better Handle Designs with Datapaths, in Proc. ISPD, 2012.

Digital Library

[19]

S. Ward, D. Ding, D. Z. Pan, PADE: A High-Performance Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning, in Proc. DAC, 2012.

Digital Library

Cited By

Wang ZHe ZBai CYang HYu B(2023)Efficient Arithmetic Block Identification With Graph Learning and Network-FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322781542:8(2591-2603)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3227815
Singh AMishra VAkhter S(2023)Investigating Machine Learning Applications for FDSOI MOS-Based Computer-Aided Design2023 9th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC60394.2023.10441540(708-713)Online publication date: 21-Dec-2023
https://doi.org/10.1109/ICSC60394.2023.10441540
He ZWang ZBail CYang HYu B(2021)Graph Learning-Based Arithmetic Block Identification2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643581(1-8)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643581
Show More Cited By

Index Terms

Network flow based datapath bit slicing
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

Recommendations

Graph-Based Logic Bit Slicing for Datapath-Aware Placement
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Extracting similar datapath bit slices which handle highly parallel bit operations can help a modern placer to obtain better solutions for datapath-oriented designs. A current state-of-the-art datapath bit slicing method achieves the best extraction ...
Keep it straight: teaching placement how to better handle designs with datapaths
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell components. This work begins by demonstrating that conventional Half-...
Structure-aware placement for datapath-intensive circuit designs
DAC '12: Proceedings of the 49th Annual Design Automation Conference

Datapath is one of the most important components in high performance circuit designs, such as microprocessors, as it is used to manipulate all data. For better performance, a datapath is usually placed with high regularity and compactness. Although cell ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 March 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISPD'13

Sponsor:

SIGDA

ISPD'13: International Symposium on Physical Design

March 24 - 27, 2013

Nevada, Stateline, USA

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
320
Total Downloads

Downloads (Last 12 months)21
Downloads (Last 6 weeks)2

Reflects downloads up to 28 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Wang ZHe ZBai CYang HYu B(2023)Efficient Arithmetic Block Identification With Graph Learning and Network-FlowIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322781542:8(2591-2603)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3227815
Singh AMishra VAkhter S(2023)Investigating Machine Learning Applications for FDSOI MOS-Based Computer-Aided Design2023 9th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC60394.2023.10441540(708-713)Online publication date: 21-Dec-2023
https://doi.org/10.1109/ICSC60394.2023.10441540
He ZWang ZBail CYang HYu B(2021)Graph Learning-Based Arithmetic Block Identification2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643581(1-8)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643581
Sotiriou CSketopoulos NNayak APenzes P(2019)Extraction of Structural Regularity for Random Logic Netlists2019 Panhellenic Conference on Electronics & Telecommunications (PACET)10.1109/PACET48583.2019.8956275(1-7)Online publication date: Nov-2019
https://doi.org/10.1109/PACET48583.2019.8956275
Lin YPan D(2019)Machine Learning in Physical Verification, Mask Synthesis, and Physical DesignMachine Learning in VLSI Computer-Aided Design10.1007/978-3-030-04666-8_4(95-115)Online publication date: 16-Mar-2019
https://doi.org/10.1007/978-3-030-04666-8_4
Huang CLin BLee HChang YWu KYang J(2017)Graph-Based Logic Bit Slicing for Datapath-Aware PlacementProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062254(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062254
Cho MChoudhury MPuri RRen HXiang HNam GMo FBrayton R(2016)Structured Digital DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-9(155-182)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-9
Yu BPan DMatsunawa TZeng X(2015)Machine learning and pattern matching in physical designThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059020(286-293)Online publication date: Jan-2015
https://doi.org/10.1109/ASPDAC.2015.7059020
Puri RChoudhury MQian HZiegler MXie YKarnik TKhellah MMehra R(2014)Bridging high performance and low power in processor designProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2631642(183-188)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2631642
Ziegler MPuri RPhilhower BFranch RLuk WLeenstra JVerwegen PFricke NGristede GFluhr EZyuban V(2014)POWER8 design methodology innovations for improving productivity and reducing powerProceedings of the IEEE 2014 Custom Integrated Circuits Conference10.1109/CICC.2014.6946042(1-9)Online publication date: Sep-2014
https://doi.org/10.1109/CICC.2014.6946042
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten