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Network flow based datapath bit slicing

Published: 24 March 2013 Publication History

Abstract

In deep sub-micro designs, more functions are integrated into one chip, and datapath has become a critical part of the design. Typical datapath consists an array of bit slices. The inherent high degree regularity of datapaths is especially attractive to the placement and routing to achieve regular layout with high density and high performance. However, the current design methodology may generate inferior datapath designs because the datapath regularity cannot be well understood by the traditional design tools. In previous works, several techniques are proposed to preserve/re-identify datapath structures. However, they either restrict the datapath optimization or have little tolerance on bit slice difference.
In this work, we present a novel approach to re-identify datapath bit slices. Contrary to the previous template-based approach, we convert the bit slicing problem to the bit matching problem. Then a min-cost max-flow based algorithm is proposed to identify the main-frame of bit slices so that the datapath bit matching is achieved. An efficient two way search approach is developed to derive the full bit slices based on the bit matching results. We further improve the bit slicing solution with an iterative method. The experimental results demonstrate the effectiveness and efficiency of our approach.

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cover image ACM Conferences
ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design
March 2013
194 pages
ISBN:9781450319546
DOI:10.1145/2451916
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 March 2013

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Author Tags

  1. bit slicing
  2. datapath
  3. network flow

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ISPD'13
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ISPD'13: International Symposium on Physical Design
March 24 - 27, 2013
Nevada, Stateline, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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  • (2023)Investigating Machine Learning Applications for FDSOI MOS-Based Computer-Aided Design2023 9th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC60394.2023.10441540(708-713)Online publication date: 21-Dec-2023
  • (2021)Graph Learning-Based Arithmetic Block Identification2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643581(1-8)Online publication date: 1-Nov-2021
  • (2019)Extraction of Structural Regularity for Random Logic Netlists2019 Panhellenic Conference on Electronics & Telecommunications (PACET)10.1109/PACET48583.2019.8956275(1-7)Online publication date: Nov-2019
  • (2019)Machine Learning in Physical Verification, Mask Synthesis, and Physical DesignMachine Learning in VLSI Computer-Aided Design10.1007/978-3-030-04666-8_4(95-115)Online publication date: 16-Mar-2019
  • (2017)Graph-Based Logic Bit Slicing for Datapath-Aware PlacementProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062254(1-6)Online publication date: 18-Jun-2017
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  • (2015)Machine learning and pattern matching in physical designThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059020(286-293)Online publication date: Jan-2015
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  • (2014)POWER8 design methodology innovations for improving productivity and reducing powerProceedings of the IEEE 2014 Custom Integrated Circuits Conference10.1109/CICC.2014.6946042(1-9)Online publication date: Sep-2014
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