research-article

Multiple chip planning for chip-interposer codesign

Authors:

Yao-Wen ChangAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 27, Pages 1 - 6

https://doi.org/10.1145/2463209.2488767

Published: 29 May 2013 Publication History

Abstract

An interposer-based three-dimensional integrated circuit, which introduces a silicon interposer as an interface between chips and a package, is one of the most promising integration technologies for modern and next-generation circuit designs. Inter-chip connections can be routed on the interposer by chip-scale wires to enhance design quality. However, its design complexity increases dramatically due to the extra interposer interface. Consequently, it is desirable to simultaneously consider the co-design of the interposer and multiple chips mounted on it. This paper addresses the first work of chip-interposer codesign to place multiple chips on an interposer to reduce inter-chip wirelength. For this problem, we propose a new hierarchical B*-tree to simultaneously place multiple chips, macros, and I/O Buffers. An approach based on bipartite matching is then proposed to concurrently assign signals from I/O buffers to micro bumps. Experimental results show that our approach is effective and efficient for the codesign problem.

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Cited By

Yang ZDeng LLi CZhang L(2025)Optimization of Built-In Self-Test test chain configuration in 2.5D Integrated Circuits Using Constrained Multi-Objective Evolutionary AlgorithmEngineering Applications of Artificial Intelligence10.1016/j.engappai.2024.109876143(109876)Online publication date: Mar-2025
https://doi.org/10.1016/j.engappai.2024.109876
Chang YHui-Ru Jiang IPosser G(2024)Physical Design Challenges in Modern Heterogeneous IntegrationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3639690(125-134)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3639690
Sangiovanni-Vincentelli ALiang ZZhou ZZhang JChinnery DHui-Ru Jiang I(2023)Automated Design of ChipletsProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3578917(1-8)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3578917
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Index Terms

Multiple chip planning for chip-interposer codesign
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Yang ZDeng LLi CZhang L(2025)Optimization of Built-In Self-Test test chain configuration in 2.5D Integrated Circuits Using Constrained Multi-Objective Evolutionary AlgorithmEngineering Applications of Artificial Intelligence10.1016/j.engappai.2024.109876143(109876)Online publication date: Mar-2025
https://doi.org/10.1016/j.engappai.2024.109876
Chang YHui-Ru Jiang IPosser G(2024)Physical Design Challenges in Modern Heterogeneous IntegrationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3639690(125-134)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3639690
Sangiovanni-Vincentelli ALiang ZZhou ZZhang JChinnery DHui-Ru Jiang I(2023)Automated Design of ChipletsProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3578917(1-8)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3578917
Lin JTsai TTsai T(2023)Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in PackageIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.329138131:9(1308-1319)Online publication date: Sep-2023
https://doi.org/10.1109/TVLSI.2023.3291381
Lee CChang Y(2023)Floorplanning for Embedded Multi-Die Interconnect Bridge Packages2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323609(1-8)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323609
Zhi CDong GWang YZhu ZYang Y(2022)Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise EliminationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.320041069:12(5247-5258)Online publication date: Dec-2022
https://doi.org/10.1109/TCSI.2022.3200410
Yan J(2021)Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.311391829:11(1889-1902)Online publication date: Nov-2021
https://doi.org/10.1109/TVLSI.2021.3113918
Chiang CChuang FChang YCheng KYang H(2020)Unified Redistribution Layer Routing for 2.5D IC PackagesProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045359(331-337)Online publication date: 17-Jan-2020
https://dl.acm.org/doi/10.1109/ASP-DAC47756.2020.9045359
Dadashi SReza AReshadi MKhademzadeh A(2019)Decreasing latency considering power consumption issue in silicon interposer-based network-on-chipThe Journal of Supercomputing10.1007/s11227-019-02964-wOnline publication date: 21-Aug-2019
https://doi.org/10.1007/s11227-019-02964-w
Osmolovskyi SKnechtel JMarkov ILienig JShin Y(2018)Optimal die placement for interposer-based 3D ICsProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201729(513-520)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201729
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