research-article

A heterogeneous multiple network-on-chip design: an application-aware approach

Authors:

Asit K. Mishra,

Chita R. DasAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 36, Pages 1 - 10

https://doi.org/10.1145/2463209.2488779

Published: 29 May 2013 Publication History

Abstract

Current network-on-chip designs in chip-multiprocessors are agnostic to application requirements and hence are provisioned for the general case, leading to wasted energy and performance. We observe that applications can generally be classified as either network bandwidth-sensitive or latency-sensitive. We propose the use of two separate networks on chip, where one network is optimized for bandwidth and the other for latency, and the steering of applications to the appropriate network. We further observe that not all bandwidth (latency) sensitive applications are equally sensitive to network bandwidth (latency). Hence, within each network, we prioritize packets based on the relative sensitivity of the applications they belong to. We introduce two metrics, network episode height and length, as proxies to estimate bandwidth and latency sensitivity, to classify and rank applications. Our evaluations show that the resulting heterogeneous two-network design can provide significant energy savings and performance improvements across a variety of workloads compared to a single one-size-fits-all single network and homogeneous multiple networks.

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Cited By

Gonzalez-Martinez GSandoval-Arechiga RSolis-Sanchez LGarcia-Luciano LIbarra-Delgado SSolis-Escobedo JGomez-Rodriguez JRodriguez-Abdala V(2024)A Survey of MPSoC Management toward Self-AwarenessMicromachines10.3390/mi1505057715:5(577)Online publication date: 26-Apr-2024
https://doi.org/10.3390/mi15050577
Yang JZheng HLouri A(2024)Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN AccelerationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.334095335:2(349-361)Online publication date: Feb-2024
https://doi.org/10.1109/TPDS.2023.3340953
Jiang FLi CChen LLiu JZhang WXu J(2024)SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473870(13-18)Online publication date: 22-Jan-2024
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Index Terms

A heterogeneous multiple network-on-chip design: an application-aware approach
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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https://doi.org/10.3390/mi15050577
Yang JZheng HLouri A(2024)Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN AccelerationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.334095335:2(349-361)Online publication date: Feb-2024
https://doi.org/10.1109/TPDS.2023.3340953
Jiang FLi CChen LLiu JZhang WXu J(2024)SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473870(13-18)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473870
Yadav SLaxmi VKapoor HGaur MKumar A(2023)Adaptive distribution of control messages for improving bandwidth utilization in multiple NoCThe Journal of Supercomputing10.1007/s11227-023-05208-079:15(17208-17246)Online publication date: 7-May-2023
https://doi.org/10.1007/s11227-023-05208-0
Zheng HLouri A(2022)Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip DesignIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.300349610:1(223-236)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TETC.2020.3003496
Batra NSingh B(2022)Evolution of Efficient On-Chip Interconnect Architecture for SOC: A Review2022 IEEE Global Conference on Computing, Power and Communication Technologies (GlobConPT)10.1109/GlobConPT57482.2022.9938209(1-6)Online publication date: 23-Sep-2022
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Li YLouri A(2021)ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore ArchitecturesIEEE Transactions on Sustainable Computing10.1109/TSUSC.2020.29813406:2(274-288)Online publication date: 1-Apr-2021
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Zheng HWang KLouri A(2021)Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00066(723-735)Online publication date: Feb-2021
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Cohen LRowe R(2020)Non-well-founded Proof Theory of Transitive Closure LogicACM Transactions on Computational Logic10.1145/340488921:4(1-31)Online publication date: 11-Aug-2020
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