skip to main content
10.1145/2463209.2488780acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Designing energy-efficient NoC for real-time embedded systems through slack optimization

Published: 29 May 2013 Publication History

Abstract

Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to minimize the energy consumption of NoC without violating the pre-specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline---the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-efficiency, while meeting the deadlines for all packets.

References

[1]
L. Benini and G. D. Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70--78, 2002.
[2]
T. Bjerregaard and J. Sparso. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In DATE, pages 1226--1231, 2005.
[3]
J.-Y. L. Boudec and P. Thiran, editors. Network Calculus: A Theory of Deterministic Queuing Systems for the Internet. Lecture Notes in Computer Science. Springer-Verlag, Berlin, Heidelberg, 2001.
[4]
S. Chakraborty, S. Kunzli, and L. Thiele. A general framework for analysing system properties in platform-based embedded system designs. In DATE, pages 190--195, Munich, Germany, 2003.
[5]
C.-S. Chang, editor. Performance Guarantees in Communication networks, pages 78--83. Springer-Verlag, London, UK, 2000.
[6]
W. Dally and S. Tell. The even/odd synchronizer: A fast, all-digital, periodic synchronizer. In ASYNC, pages 75--84, 2010.
[7]
W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In DAG, pages 684--689, 2001.
[8]
W. J. Dally and B. Towles, editors. Principles and Pracitices of Interconnection Networks, pages 245--247. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2003.
[9]
R. Das, O. Mutlu, T. Moscibroda, and C. R. Das. Aergia: exploiting packet latency slack in on-chip networks. In ISCA, pages 106--116, 2010.
[10]
K. Goossens, J. Dielissen, and A. Radulescu. Æthereal network on chip: concepts, architectures, and implementations. Design & Test of Computers, IEEE, 22(5):414--421, 2005.
[11]
K. Goossens and A. Hansson. The Æthereal network on chip after ten years: Goals, evolution, lessons, and future. In DAC, pages 306--311, 2010.
[12]
N. Jiang, G. Michelogiannakis, D. Becker, B. Towles, and W. J. Dally. BookSim 2.0 User's Guide. Standford University, 2010.
[13]
A. B. Kahng, B. Li, L.-S. Peh, and K. Samadi. ORION 2.0: A power-area simulator for interconnection networks. IEEE Trans, on VLSI, pages 191--196, 2012.
[14]
D. Lackey, P. Zuchowski, T. Bednar, D. Stout, S. Gould, and J. Cohn. Managing power and performance for system-on-chip designs using voltage islands. In ICCAD, pages 195--202, 2002.
[15]
A. K. Mishra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan, and C. R. Das. A case for dynamic frequency tuning in on-chip networks. In MICRO, pages 292--303, 2009.
[16]
K. Niyogi and D. Marculescu. Speed and voltage selection for GALS systems based on voltage/frequency islands. In ASPDAC, pages 292--297, 2005.
[17]
U. Ogras, R. Marculescu, D. Marculescu, and E. G. Jung. Design and management of voltage-frequency island partitioned networks-on-chip. IEEE Trans, on VLSI, 17(3):330--341, 2009.
[18]
Y. Qian, Z. Lu, and W. Dou. Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip. In NOCS, pages 44--53, 2009.
[19]
L. Shang, L.-S. Peh, and N. K. Jha. Dynamic voltage scaling with links for power optimization of interconnection networks. In HPCA, pages 91--102, 2003.
[20]
A. Sharifi, H. Zhao, and M. Kandemir. Feedback control for providing QoS in NoC based multicores. In DATE, pages 1384--1389, 2010.
[21]
P. Zhou, J. Yin, A. Zhai, and S. S. Sapatnekar. NoC frequency scaling with flexible-pipeline routers. In ISLPED, pages 403--408, 2011.

Cited By

View all
  • (2023)Slack-Aware Packet Approximation for Energy-Efficient Network-on-ChipsIEEE Transactions on Sustainable Computing10.1109/TSUSC.2022.32134698:1(120-132)Online publication date: 1-Jan-2023
  • (2018)Prototyping self-managed interdependent networksProceedings of the 13th International Conference on Software Engineering for Adaptive and Self-Managing Systems10.1145/3194133.3194148(119-129)Online publication date: 28-May-2018
  • (2018)adBoost: Thermal Aware Performance Boosting Through Dark Silicon PatterningIEEE Transactions on Computers10.1109/TC.2018.280568367:8(1062-1077)Online publication date: 1-Aug-2018
  • Show More Cited By

Index Terms

  1. Designing energy-efficient NoC for real-time embedded systems through slack optimization

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '13: Proceedings of the 50th Annual Design Automation Conference
    May 2013
    1285 pages
    ISBN:9781450320719
    DOI:10.1145/2463209
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    In-Cooperation

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 29 May 2013

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. network calculus
    2. network-on-chip
    3. voltage-frequency scaling

    Qualifiers

    • Research-article

    Conference

    DAC '13
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)6
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 08 Mar 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2023)Slack-Aware Packet Approximation for Energy-Efficient Network-on-ChipsIEEE Transactions on Sustainable Computing10.1109/TSUSC.2022.32134698:1(120-132)Online publication date: 1-Jan-2023
    • (2018)Prototyping self-managed interdependent networksProceedings of the 13th International Conference on Software Engineering for Adaptive and Self-Managing Systems10.1145/3194133.3194148(119-129)Online publication date: 28-May-2018
    • (2018)adBoost: Thermal Aware Performance Boosting Through Dark Silicon PatterningIEEE Transactions on Computers10.1109/TC.2018.280568367:8(1062-1077)Online publication date: 1-Aug-2018
    • (2018)Supporting Dynamic Voltage and Frequency Scaling in Networks-On-Chip for Hard Real-Time Systems2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA.2018.00024(125-135)Online publication date: Aug-2018
    • (2018)Power and Energy Characterization of an Open Source 25-Core Manycore Processor2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00070(762-775)Online publication date: Feb-2018
    • (2017)A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in SimulinkACM Transactions on Modeling and Computer Simulation10.1145/300544627:3(1-26)Online publication date: 24-Aug-2017
    • (2017)Survey on Real-Time Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262361928:5(1500-1517)Online publication date: 1-May-2017
    • (2017)Self-Repairable Smart Grids Via Online Coordination of Smart TransformersIEEE Transactions on Industrial Informatics10.1109/TII.2016.262504113:4(1783-1793)Online publication date: Aug-2017
    • (2017)Network-on-Chip DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_16(461-489)Online publication date: 27-Sep-2017
    • (2016)Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253674724:10(3041-3054)Online publication date: 1-Oct-2016
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media