research-article

ABCD-L: approximating continuous linear systems using boolean models

Authors:

Aadithya V. Karthik,

Jaijeet RoychowdhuryAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 63, Pages 1 - 9

https://doi.org/10.1145/2463209.2488811

Published: 29 May 2013 Publication History

Abstract

We present ABCD-L, a scalable technique for Analog/Mixed Signal (AMS) modelling/verification that captures the continuous dynamics of Linear Time-Invariant (LTI) systems, using purely Boolean approximations, to any desired level of accuracy. ABCD-L's models can be used in conjunction with existing techniques for Boolean synthesis/verification/fast logic simulation, or with hybrid systems frameworks, to represent LTI dynamics without incurring the penalty of adding continuous variables. Unlike existing state-enumeration approaches like DAE2FSM [1], ABCD-L scales practically linearly with system size. We apply ABCD-L to I/O links composed of RC/RLGC units, capturing important analog effects like inter-symbol interference, overshoot/undershoot, ringing, etc. -- all using purely Boolean models. We also present a continuous-time differential equalizer example, where ABCD-L accurately reproduces key design-relevant AMS metrics, including the eye diagram correction achieved by the circuit. Furthermore, for real-world LTI systems, we demonstrate that ABCD-L can be applied in conjunction with Model Order Reduction (MOR) techniques; we use this to produce accurate Boolean models of an industry-scale power grid network (with 25849 nodes) made available by IBM. We also demonstrate that Boolean simulation using ABCD-L's models offers considerable speed-up over standard circuit simulation using linear multi-step numerical methods.

References

[1]

A. Ghosh and R. Vemuri. Formal verification of synthesized analog designs. In ICCD '99: Proceedings of the IEEE International Conference on Computer Design, pages 40--45, 1999.

Digital Library

[2]

K. Hanna. Reasoning about real circuits. In Proceedings of the 7^th International Workshop on Higher Order Logic Theorem Proving and Its Applications, pages 235--253, 1994.

Digital Library

[3]

K. Hanna. Reasoning about analog-level implementations of digital systems. Formal Methods in System Design, 16(2):127--158, 2000.

Digital Library

[4]

R. P. Kurshan and K. L. McMillan. Analysis of digital circuits through symbolic reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(11):1356--1371, 1991.

Digital Library

[5]

W. Hartong, L. Hedrich, and E. Barke. Model checking algorithms for analog verification. In DAC '02: Proceedings of the 39^th annual ACM Design Automation Conference, pages 542--547, 2002.

Digital Library

[6]

S. Steinhorst and L. Hedrich. Model checking of analog systems using an analog specification language. In DATE '08: Proceedings of the ACM Conference on Design, Automation and Test in Europe, pages 324--329, 2008.

Digital Library

[7]

R. Alur, C. Courcoubetis, T. A. Henzinger, and P. H. Ho. Hybrid automata: An algorithmic approach to the specification and verification of hybrid systems. Hybrid Systems, pages 209--229, 1993.

Digital Library

[8]

A. Nerode and W. Kohn. Models for hybrid systems: Automata, topologies, controllability, observability. Hybrid Systems, pages 317--356, 1993.

Digital Library

[9]

R. Alur, C. Courcoubetis, N. Halbwachs, T. A. Henzinger, P. H. Ho, X. Nicollin, A. Olivero, J. Sifakis, and S. Yovine. The algorithmic analysis of hybrid systems. Theoretical Computer Science, 138(1):3--34, 1995.

Digital Library

[10]

T. A. Henzinger. The theory of hybrid automata. In LICS '96: Proceedings of the 11^th Annual IEEE Symposium on Logic in Computer Science, pages 278--292, 1996.

Digital Library

[11]

G. Al-Sammane, M. H. Zaki, and S. Tahar. A symbolic methodology for the verification of AMS designs. In DATE '07: Proceedings of the ACM Conference on Design, Automation and Test in Europe, pages 249--254, 2007.

Digital Library

[12]

M. H. Zaki, G. Al-Sammane, S. Tahar, and G. Bois. Combining symbolic simulation and interval arithmetic for the verification of AMS designs. In FMCAD '07: Formal Methods in Computer Aided Design, pages 207--215, 2007. th

Digital Library

[13]

E. Asarin, T. Dang, and O. Maler. d/dt: A verification tool for hybrid systems. In CDC '01: Proceedings of the 40^th IEEE Conference on Decision and Control, pages 2893--2898, 2001.

[14]

S. Ray, J. Bhadra, T. Portlock, and R. Syzdek. Modeling and verification of industrial flash memories. In ISQED '10: Proceedings th of the 11^th International Symposium on Quality Electronic Design, pages 705--712, 2010.

[15]

T. A. Henzinger, P. H. Ho, and H. Wong-Toi. HyTech: A model checker for hybrid systems. International Journal on Software Tools for Technology Transfer, 1(1):110--122, 1997.

Digital Library

[16]

G. Frehse. PHAVer: Algorithmic verification of hybrid systems past HyTech. International Journal on Software Tools for Technology Transfer, 10(3):263--279, 2008.

Digital Library

[17]

A. Chutinan and B. H. Krogh. Computational techniques for hybrid system verification. IEEE Transactions on Automatic Control, 48(1):64--75, 2003.

[18]

S. Little, N. Seegmiller, D. Walter, C. Myers, and T. Yoneda. Verification of ams circuits using labeled hybrid petri nets. In ICCAD '06: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 275--282, 2006.

Digital Library

[19]

S. Little, D. Walter, K. Jones, and C. Myers. AMS circuit verification using models generated from simulation traces. Automated Technology for Verification and Analysis, pages 114--128, 2007.

Digital Library

[20]

S. Little. Efficient Modeling and Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. PhD thesis, University of Utah, 2008.

Digital Library

[21]

S. Batchu. Automatic Extraction of Behavioral Models from Simulations of Analog/Mixed-Signal (AMS) Circuits. Master's thesis, University of Utah, 2010.

[22]

M. Althoff, O. Stursberg, and M. Buss. Computing reachable sets of hybrid systems using a combination of zonotopes and polytopes. Nonlinear Analysis: Hybrid Systems, 4(2):233--249, 2010.

[23]

F. Wang. Symbolic parametric safety analysis of linear hybrid systems with BDD-like data-structures. IEEE Transactions on Software Engineering, 31(1):38--51, 2005.

Digital Library

[24]

C. Le Guernic and A. Girard. Reachability analysis of hybrid systems using support functions. In CAV '09: Proceedings of the International Conference on Computer Aided Verification, pages 540--554, 2009.

Digital Library

[25]

M. Althoff, A. Rajhans, B. H. Krogh, S. Yaldiz, X. Li, and L. Pileggi. Formal verification of Phase Locked Loops using reachability analysis and continuization. In ICCAD '10: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 659--666, 2010.

Digital Library

[26]

L. T. Pillage and R. A. Rohrer. Asymptotic waveform evaluation for timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):352--366, 1990.

Digital Library

[27]

K. J. Kerns, I. L. Wemple, and A. T. Yang. Stable and efficient reduction of substrate model networks using congruence transforms. In ICCAD '95: Proceedings of the IEEE/ACM International Conference on Computer-Aided design, pages 207--214, 1995.

Digital Library

[28]

P. Feldmann and R. W. Freund. Efficient linear circuit analysis by Padé approximation via the Lanczos process. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(5):639--649, 1995.

Digital Library

[29]

L. Silveira, M. Kamon, I. Elfadel, and J. White. A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. Computer Methods in Applied Mechanics and Engineering, 169(3):377--389, 1999.

[30]

A. Odabasioglu, M. Celik, and L. T. Pileggi. Prima: Passive reduced-order interconnect macromodeling algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(8):645--654, 1998. th

Digital Library

[31]

S. R. Nassif. Power grid analysis benchmarks. In ASPDAC '08: Proceedings of the 13^th IEEE/ACM Asia and South Pacific Design Automation Conference, pages 376--381, 2008.

Digital Library

[32]

Download link for the IBM power grid benchmark set: http://dropzone.tamu.edu/~pli/PGBench/.

[33]

W. E. Arnoldi. The principle of minimized iterations in the solution of the matrix eigenvalue problem. The Quarterly of Applied Mathematics, 9(1):17--29, 1951.

[34]

W. H. A. Schilders, H. A. van der Vorst, and J. Rommes. Model Order Reduction: Theory, research aspects and applications, volume 13 of Mathematics in Industry. Springer Verlag, 2008.

Cited By

Balszun MHobbs CFraccaroli ERoy DFummi FChakraborty S(2022)Process Dynamics-Aware Flexible Manufacturing for Industry 4.02022 IEEE 18th International Conference on Automation Science and Engineering (CASE)10.1109/CASE49997.2022.9926495(2375-2382)Online publication date: 20-Aug-2022
https://doi.org/10.1109/CASE49997.2022.9926495
Bidmeshki MAntonopoulos AMakris Y(2021)Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal DesignsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.307509811:2(415-427)Online publication date: Jun-2021
https://doi.org/10.1109/JETCAS.2021.3075098
Jeličić GBöswald MBrandt A(2021)Improved computation in terms of accuracy and speed of LTI system response with arbitrary inputMechanical Systems and Signal Processing10.1016/j.ymssp.2020.107252150(107252)Online publication date: Mar-2021
https://doi.org/10.1016/j.ymssp.2020.107252
Show More Cited By

Index Terms

ABCD-L: approximating continuous linear systems using boolean models
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation

Recommendations

ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips
VLSID '05: Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single / multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the ...
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model
DFT '04: Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium

The paper describes an ABCD modeling approach of a victim interconnect that takes into account the crosstalk coupling effect due to aggressor line in deep sub-micron chips. After the order reduction the crosstalk model is utilized for the analysis of ...
Analysis of power-performance for ultra-thin-body GeOI logic circuits
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

This work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
211
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Balszun MHobbs CFraccaroli ERoy DFummi FChakraborty S(2022)Process Dynamics-Aware Flexible Manufacturing for Industry 4.02022 IEEE 18th International Conference on Automation Science and Engineering (CASE)10.1109/CASE49997.2022.9926495(2375-2382)Online publication date: 20-Aug-2022
https://doi.org/10.1109/CASE49997.2022.9926495
Bidmeshki MAntonopoulos AMakris Y(2021)Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal DesignsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.307509811:2(415-427)Online publication date: Jun-2021
https://doi.org/10.1109/JETCAS.2021.3075098
Jeličić GBöswald MBrandt A(2021)Improved computation in terms of accuracy and speed of LTI system response with arbitrary inputMechanical Systems and Signal Processing10.1016/j.ymssp.2020.107252150(107252)Online publication date: Mar-2021
https://doi.org/10.1016/j.ymssp.2020.107252
Deyati SMuldrey BChatterjee A(2020)Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From HardwareIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294890239:10(2006-2019)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2948902
Dghais WSouilem MAlam M(2019)Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity AssessmentIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.288540727:3(691-699)Online publication date: Mar-2019
https://doi.org/10.1109/TVLSI.2018.2885407
Antonopoulos AKapatsori CMakris Y(2017)Trusted Analog/Mixed- Signal/RF ICs: A Survey and a PerspectiveIEEE Design & Test10.1109/MDAT.2017.272836634:6(63-76)Online publication date: Dec-2017
https://doi.org/10.1109/MDAT.2017.2728366
Antonopoulos AKapatsori CMakris Y(2017)Security and trust in the analog/mixed-signal/RF domain: A survey and a perspective2017 22nd IEEE European Test Symposium (ETS)10.1109/ETS.2017.7968235(1-10)Online publication date: May-2017
https://doi.org/10.1109/ETS.2017.7968235
Antonopoulos AKapatsori CMakris Y(2017)Hardware Trojans in Analog, Mixed-Signal, and RF ICsThe Hardware Trojan War10.1007/978-3-319-68511-3_5(101-123)Online publication date: 30-Nov-2017
https://doi.org/10.1007/978-3-319-68511-3_5
Deyati SMuldrey BChatterjee A(2016)Adaptive testing of analog/RF circuits using hardware extracted FSM models2016 IEEE 34th VLSI Test Symposium (VTS)10.1109/VTS.2016.7477283(1-6)Online publication date: Apr-2016
https://doi.org/10.1109/VTS.2016.7477283
Deyati SMuldrey BChatterjee A(2016)TRAPProceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2016.118(463-468)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1109/VLSID.2016.118
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten