research-article

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis

Authors:

Chris J. MyersAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 66, Pages 1 - 6

https://doi.org/10.1145/2463209.2488814

Published: 29 May 2013 Publication History

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis

Pages 1 - 6

Abstract
References

Abstract

The emergence of digitally-intensive analog circuits introduces new challenges to formal verification due to increased digital design content, and non-ideal digital effects such as finite resolution, round-off error and overflow. We propose a machine learning approach to convert digital blocks to conservative analog approximations via the use of kernel ridge regression. These learned models are then adopted in a hybrid formal reachability analysis framework where the support function based manipulations are developed to efficiently handle the large linear portion of the design and the more general satisfiability modulo theories technique is applied to the remaining nonlinear portion. The efficiency of the proposed method is demonstrated for the locked time verification of a digitally intensive phase locked loop.

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Cited By

Kim SKim J(2023)Reachability Analysis for Nonlinear Analog/Mixed-Signal Circuits With Trajectory-Based Reachable SetsIEEE Access10.1109/ACCESS.2023.329582511(74602-74613)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3295825
Lei JChatterjee A(2022)ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00035(268-277)Online publication date: Sep-2022
https://doi.org/10.1109/ITC50671.2022.00035
Muldrey BBanerjee SChatterjee A(2019)Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery2019 IEEE 37th VLSI Test Symposium (VTS)10.1109/VTS.2019.8758673(1-6)Online publication date: Apr-2019
https://doi.org/10.1109/VTS.2019.8758673
Show More Cited By

Index Terms

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis
1. Hardware

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Kim SKim J(2023)Reachability Analysis for Nonlinear Analog/Mixed-Signal Circuits With Trajectory-Based Reachable SetsIEEE Access10.1109/ACCESS.2023.329582511(74602-74613)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3295825
Lei JChatterjee A(2022)ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00035(268-277)Online publication date: Sep-2022
https://doi.org/10.1109/ITC50671.2022.00035
Muldrey BBanerjee SChatterjee A(2019)Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery2019 IEEE 37th VLSI Test Symposium (VTS)10.1109/VTS.2019.8758673(1-6)Online publication date: Apr-2019
https://doi.org/10.1109/VTS.2019.8758673
Tao JLiao CZeng XLi X(2016)Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244924035:1(23-36)Online publication date: Jan-2016
https://doi.org/10.1109/TCAD.2015.2449240
ul Asad HJones K(2015)Verifying inevitability of phase-locking in a charge pump phase lock loop using sum of squares programmingProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744926(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744926
Asad HJones KJones ALi HCoskun AMargala M(2015)Inevitability of Phase-locking in a Charge Pump Phase Lock Loop using Deductive VerificationProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742072(295-300)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742072
Peng YGreenstreet M(2015)Integrating SMT with Theorem Proving for Analog/Mixed-Signal Circuit VerificationNASA Formal Methods10.1007/978-3-319-17524-9_22(310-326)Online publication date: 8-Apr-2015
https://doi.org/10.1007/978-3-319-17524-9_22
Lin HLi P(2014)Parallel Hierarchical Reachability Analysis for Analog VerificationProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593178(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593178
Jijie Wei Yan Peng Ge Yu Greenstreet M(2013)Verifying global convergence for a digital phase-locked loop2013 Formal Methods in Computer-Aided Design10.1109/FMCAD.2013.6679399(113-120)Online publication date: Oct-2013
https://doi.org/10.1109/FMCAD.2013.6679399

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