research-article

Lighting the dark silicon by exploiting heterogeneity on future processors

Authors:

Yue HuAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 82, Pages 1 - 7

https://doi.org/10.1145/2463209.2488835

Published: 29 May 2013 Publication History

Abstract

As we embrace the deep submicron era, dark silicon caused by the failure of Dennard scaling impedes us from attaining commensurate performance benefit from the increased number of transistors. To alleviate the dark silicon and effectively leverage the advantage of decreased feature size, we consider a set of design paradigms by exploiting heterogeneity in the processor manufacturing. We conduct a thorough investigation on these design patterns from different evaluation perspectives including performance, energy-efficiency, and cost-efficiency. Our observations can provide insightful guidance to the design of future processors in the presence of dark silicon.

References

[1]

Intel Corporation. High-K and Metal Gate Transistor Research. http://www.intel.com/pressroom/kits/advancedtech/doodle/ref_HiK-MG/high-k.htm

[2]

Intel Corporation. Ivy Bridge Products. http://ark.intel.com/products/codename/29902/Ivy-Bridge

[3]

International Technology Roadmap for Semiconductors. http://www.itrs.net/

[4]

Hotspot 5.0 Temperature Modeling Tool. http://lava.cs.virginia.edu/HotSpot/.

[5]

Global Semiconductor Alliance. http://www.gsaglobal.org

[6]

H. F. Dadgour and K. Banerjee. Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications. In DAC'07.

Digital Library

[7]

R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. Near-threshold computing: reclaiming Moore's law through energy efficient circuit. Proceedings of the IEEE, special issue on ultra-low power circuit technology, Feb. 2010.

[8]

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger. Dark silicon and the end of multicore scaling. In ISCA'11.

Digital Library

[9]

V. Gupta et al. Using heterogeneous cores to provide a high dynamic power range on over-provisioned processors. In Dark Silicon Workshop in conjunction with ISCA, Jun. 2012.

[10]

N. Hardavellas, M. Ferdman, B. Falsafi, A. Ailamaki. Toward dark silicon in servers. In IEEE Computer Society, 2011.

Digital Library

[11]

R. Jammy. Materials, process and integration options for emerging technologies. SEMATECH/ISMI symposium, 2009.

[12]

P. L-Kamran et al. Scale-out processors. In ISCA'12.

[13]

E. Kultursay et al. Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. In CODES+ISSS'12.

Digital Library

[14]

R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, D. M. Tullsen. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In MICRO'03.

Digital Library

[15]

S. Li et al. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO'09.

Digital Library

[16]

J. M. Rabaey, A. Chandrakasan and B. Nikolic. Digital Integrated Circuits, 2^nd edition.

[17]

A. Raghavan et al. Computational Sprinting. In HPCA'12.

Digital Library

[18]

J. Renau et al. SESC Simulator.

[19]

V. Saripalli et al. Exploiting heterogeneity for energy efficiency in chip multiprocessors. In IEEE Transactions on Emerging and Selected topics in Circuits and Systems, Jun. 2011.

[20]

V. Saripalli, A. K. Mishra, S. Datta and V. Narayanan. An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores, in DAC'11.

Digital Library

[21]

K. Swaminathan et al. Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores. In ISLPED'11.

Digital Library

[22]

S. Swanson et al. Area-performance trade-offs in tiled dataflow architectures. In ISCA'06.

Digital Library

[23]

M. B. Taylor. Is dark silicon useful? In DAC'12.

[24]

G. Venkatesh, J Sampson, N. Goulding, S. Garcia. Conservation cores: reducing the energy of mature computations. In ASPLOS'10.

Digital Library

[25]

G. Venkatesh et al. QSCores: Trading dark silicon for scalable energy efficiency with quasi-specific cores. In MICRO'11.

Digital Library

[26]

L. Wang, K. Skadron, and B. H. Calhoun. Dark vs. Dim silicon and near-threshold computing. In Dark Silicon Workshop in conjunction with ISCA, Jun. 2012.

[27]

X. Wu et al. Hybrid cache architecture with disparate memory technologies. In ISCA'09.

Digital Library

[28]

J. Zhao, X. Dong and Y. Xie. Cost-aware three-dimensional (3D) many-core multiprocessor design. In DAC'10.

Digital Library

Cited By

Ofori-Attah EAgyeman M(2023)An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache NodesIEEE Access10.1109/ACCESS.2022.317408411(19162-19172)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2022.3174084
Perricone RHu XNahas JNiemier M(2018)Can beyond-CMOS devices illuminate dark silicon?Communications of the ACM10.1145/323062861:9(60-69)Online publication date: 22-Aug-2018
https://dl.acm.org/doi/10.1145/3230628
Rezaei ADaneshtalab MZhou H(2018)Multiobjectivism in Dark Silicon AgeDark Silicon and Future On-chip Systems10.1016/bs.adcom.2018.03.012(83-126)Online publication date: 2018
https://doi.org/10.1016/bs.adcom.2018.03.012
Show More Cited By

Index Terms

Lighting the dark silicon by exploiting heterogeneity on future processors
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. General and reference
  1. Cross-computing tools and techniques
    1. Design

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Ofori-Attah EAgyeman M(2023)An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache NodesIEEE Access10.1109/ACCESS.2022.317408411(19162-19172)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2022.3174084
Perricone RHu XNahas JNiemier M(2018)Can beyond-CMOS devices illuminate dark silicon?Communications of the ACM10.1145/323062861:9(60-69)Online publication date: 22-Aug-2018
https://dl.acm.org/doi/10.1145/3230628
Rezaei ADaneshtalab MZhou H(2018)Multiobjectivism in Dark Silicon AgeDark Silicon and Future On-chip Systems10.1016/bs.adcom.2018.03.012(83-126)Online publication date: 2018
https://doi.org/10.1016/bs.adcom.2018.03.012
Zhao ZSrivastava APeng LChen SMohanty S(2017)A novel switchable pin method for regulating power in chip-multiprocessorIntegration10.1016/j.vlsi.2016.11.01058(329-338)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2016.11.010
Kalra PHussain SChaturvedi N(2016)An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)10.1109/iNIS.2016.023(52-55)Online publication date: Dec-2016
https://doi.org/10.1109/iNIS.2016.023
Zhan JOuyang JGe FZhao JXie Y(2016)Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253674724:10(3041-3054)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2536747
Ma JYan GHan YLi X(2016)An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous ManycoresIEEE Transactions on Computers10.1109/TC.2015.241965565:2(367-381)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TC.2015.2419655
Zhang YIrving SPeng LFu XKoppelman DZhang WArdonne J(2016)Design space exploration for device and architectural heterogeneity in chip-multiprocessorsMicroprocessors & Microsystems10.1016/j.micpro.2015.07.01240:C(88-101)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1016/j.micpro.2015.07.012
Mück TSarma SDutt NNicolescu GGerstlauer A(2015)Run-DMCProceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis10.5555/2830840.2830859(173-182)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830840.2830859
Kovacs DBisceglio JZorin D(2015)Dyadic T-mesh subdivisionACM Transactions on Graphics10.1145/276697234:4(1-12)Online publication date: 27-Jul-2015
https://dl.acm.org/doi/10.1145/2766972
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