research-article

An optimized page translation for mobile virtualization

Authors:

Yuan-Cheng Lee,

Chih-Wen HsuehAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 85, Pages 1 - 6

https://doi.org/10.1145/2463209.2488838

Published: 29 May 2013 Publication History

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Abstract

Recently, the significant progress in embedded microprocessors made it practical to support virtualization on mobile devices. Unfortunately, memory management has not been well studied in consideration of the characteristics of mobile virtualization due to the challenging aspects on both hardware and software. With a formal proof on a novel design of page translation at the second stage, we propose a novel design of page translation on both hardware and software with higher translation speed, lower variance of latency, and lower hardware complexity. The experimental results suggest it can reduce memory access by 51.37% to 56.01% as compared with the traditional approach.

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Cited By

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Zhong KLiu DWu YLong LLiu WRen JLiu RLiang LShao ZLi T(2019)Towards Fast and Lightweight Checkpointing for Mobile Virtualization Using NVRAMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.288690630:6(1421-1433)Online publication date: 1-Jun-2019
https://doi.org/10.1109/TPDS.2018.2886906
Zhong KLiu DLiang LLong LLin YShao ZFanucci LTeich J(2016)FLICProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972173(1562-1567)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972173
Shuja JGani ABilal KKhan AMadani SKhan SZomaya A(2016)A Survey of Mobile Device VirtualizationACM Computing Surveys10.1145/289716449:1(1-36)Online publication date: 5-Apr-2016
https://dl.acm.org/doi/10.1145/2897164
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An optimized page translation for mobile virtualization

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DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Zhong KLiu DWu YLong LLiu WRen JLiu RLiang LShao ZLi T(2019)Towards Fast and Lightweight Checkpointing for Mobile Virtualization Using NVRAMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.288690630:6(1421-1433)Online publication date: 1-Jun-2019
https://doi.org/10.1109/TPDS.2018.2886906
Zhong KLiu DLiang LLong LLin YShao ZFanucci LTeich J(2016)FLICProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972173(1562-1567)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972173
Shuja JGani ABilal KKhan AMadani SKhan SZomaya A(2016)A Survey of Mobile Device VirtualizationACM Computing Surveys10.1145/289716449:1(1-36)Online publication date: 5-Apr-2016
https://dl.acm.org/doi/10.1145/2897164
Lee YHsueh C(2014)A hardware evaluation of memory address translation for mobile virtualization2014 International Conference on Information Science, Electronics and Electrical Engineering10.1109/InfoSEEE.2014.6947817(992-996)Online publication date: Apr-2014
https://doi.org/10.1109/InfoSEEE.2014.6947817

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Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks

A banked-promotion translation lookaside buffer system

TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs

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