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Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Authors:

Alexander Miloslavsky,

Martin D. F. WongAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 93, Pages 1 - 6

https://doi.org/10.1145/2463209.2488848

Published: 29 May 2013 Publication History

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Abstract

Self-aligned double patterning (SADP) lithography is a leading technology for 10nm node Metal layer fabrication. In order to achieve successful decomposition, SADP-compliant design becomes a necessity. Spacer-Is-Dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. This paper makes a careful study on the challenges for SID-compliant detailed routing and proposes a graph model to capture the decomposition violations and SID intrinsic residue issues. Then a negotiated congestion based scheme is adopted to solve the overall routing problem. The proposed SID-compliant detailed routing algorithm simultaneously assigns colors to the routed wires, which provides valuable information guiding SID decomposition. In addition, if one pin has multiple candidate locations, the optimal one will be automatically determined during detailed routing. The decomposability of the conflict-free routing layers produced by our detailed router is verified by a commercial SADP decomposition tool.

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Kahng AWang LXu B(2021)TritonRoute: The Open-Source Detailed RouterIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300323440:3(547-559)Online publication date: Mar-2021
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Song YHyun DLee JJung JShin Y(2019)Cut Optimization for Redundant Via Insertion in Self-Aligned Double PatterningACM Transactions on Design Automation of Electronic Systems10.1145/335539124:6(1-21)Online publication date: 9-Sep-2019
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Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography
1. Hardware

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Published In

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Melikyan VMelikyan V(2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
https://doi.org/10.1007/978-3-031-50714-4_6
Kahng AWang LXu B(2021)TritonRoute: The Open-Source Detailed RouterIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300323440:3(547-559)Online publication date: Mar-2021
https://doi.org/10.1109/TCAD.2020.3003234
Song YHyun DLee JJung JShin Y(2019)Cut Optimization for Redundant Via Insertion in Self-Aligned Double PatterningACM Transactions on Design Automation of Electronic Systems10.1145/335539124:6(1-21)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3355391
Mantik SPosser GChow WDing YLiu WChu CBustany I(2018)ISPD 2018 Initial Detailed Routing Contest and BenchmarksProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3177562(140-143)Online publication date: 25-Mar-2018
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Ding YChu CMak W(2018)Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266037:3(657-668)Online publication date: Mar-2018
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Song YKim SShin Y(2017)Timing-aware wire width optimization for SADP processProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130762(1643-1646)Online publication date: 27-Mar-2017
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Fang SWu K(2017)Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip RoutingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.260068125:2(581-593)Online publication date: 1-Feb-2017
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Abstract

References

Cited By

Index Terms

Recommendations

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning

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