research-article

A layout-based approach for multiple event transient analysis

Authors:

Mojtaba Ebrahimi,

Mehdi B. TahooriAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 100, Pages 1 - 6

https://doi.org/10.1145/2463209.2488858

Published: 29 May 2013 Publication History

Abstract

With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout-based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is proposed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER.

References

[1]

R. C. Baumann. Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device and Materials Reliability, 5(3):305--316, 2005.

[2]

E. Ibe, H. Taniguchi, Y. Yahagi, K.-i. Shimbo, and T. Toba. Impact of scaling on neutron-induced soft error in srams from a 250 nm to a 22 nm design rule. IEEE Transactions on Electron Devices, 57(7):1527--1538, 2010.

[3]

A. Dixit and A. Wood. The impact of new technology on soft error rates. In Proceedings of the International Reliability Physics Symposium, pages 5B.4.1--5B.4.7, 2011.

[4]

H. Asadi, M. B. Tahoori, M. Fazeli, and S. G. Miremadi. Efficient algorithms to accurately compute derating factors of digital circuits. Microelectronics Reliability, pages 1215--1226, 2012.

[5]

M. Ebrahimi, L. Chen, H. Asadi, and M. B. Tahoori. Class: Combined logic and architectural soft error sensitivity analysis. In Asia and South Pacific Design Automation Conference, pages 601--607, 2013.

[6]

H. K. Lee, K. Lilja, M. Bounasser, P. Relangi, I. R. Linscott, U. S. Inan, and S. Mitra. Leap: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design. In IEEE International Reliability Physics Symposium, pages 203--212, 2010.

[7]

N. Miskov-Zivanov and D. Marculescu. Modeling and optimization for soft-error reliability of sequential circuits. IEEE Transaction on CAD of Integrated Circuits and Systems, 27(5):803--816, 2008.

Digital Library

[8]

S. Kiamehr, M. Ebrahimi, F. Firouzi, and M. B Tahoori. Chip-level modeling and analysis of electrical masking of soft errors. In VLSI Test Symposium, pages --, 2013.

[9]

A. Mohammadi, M. Ebrahimi, A. Ejlali, and S. G. Miremadi. SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model. In Proceedings of Design, Automation and Test in Europe Conference, pages 586--589, 2012.

Digital Library

[10]

D. Radaelli, H. Puchner, S. Wong, and S. Daniel. Investigation of multi-bit upsets in a 150 nm technology SRAM device. IEEE Transactions on Nuclear Science, 52(6):2433--2437, 2005.

[11]

D. Giot, P. Roche, G. Gasiot, J.-L. Autran, and R. Harboe-Sorensen. Heavy ion testing and 3-d simulations of multiple cell upset in 65 nm standard srams. IEEE Transactions on Nuclear Science, 55(4):2048--2054, 2008.

[12]

J. A. Maestro and P. Reviriego. Study of the effects of mbus on the reliability of a 150 nm sram device. In IEEE Design Automation Conference, pages 930--935, 2008.

Digital Library

[13]

R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye. Neutron induced single event multiple transients with voltage scaling and body biasing. In IEEE International Reliability Physics Symposium, pages 3C.4.1--3C.4.5, 2011.

[14]

Z. Ming, X. L. Yi, L. Chang, and Z. J. Wei. Reliability of memories protected by multi-bit error correction codes against mbus. IEEE Transactions on Nuclear Science, 58(1):289--295, 2011.

[15]

P. Reviriego, J. A. Maestro, and C. Cervantes. Reliability analysis of memories suffering multiple bit upsets. IEEE Transactions on Device and Materials Reliability, 7(4):592--601, 2007.

[16]

D. Rossi, N. Timoncini, M. Spica, and C. Metra. Error correcting code analysis for cache memory high reliability and performance. In Design, Automation & Test in Europe Conference, pages 1--6, 2011.

[17]

M. Zhang, S. Mitra, T. M. Mak, N. Seifert, N. J. Wang, Q. Shi, K. S. Kim, N. R. Shanbhag, and S. J. Patel. Sequential element design with built-in soft error resilience. IEEE Transactions on Very Large Scale Integration Systems, 14(12):1368--1378, 2006.

Digital Library

[18]

R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera. An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets. IEEE Transactions on Nuclear Science, 58(6):3053--3059, 2011.

[19]

S. Lin, H. Yang, and R. Luo. A new family of sequential elements with built-in soft error tolerance for dual-vdd systems. IEEE Transactions on Very Large Scale Integration Systems, 16(10):1372--1384, 2008.

Digital Library

[20]

M. Omana, D. Rossi, and C. Metra. High-performance robust latches. IEEE Transactions on Computers, 59(11):1455--1465, 2010.

Digital Library

[21]

B. Gill, N. Seifert, and V. Zia. Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node. In IEEE International Reliability Physics Symposium, pages 199--205, 2009.

[22]

N. N. Mahatme, S. Jagannathan, T. D. Loveless, L. W. Massengill, B. L. Bhuva, S.-J. Wen, and R. Wong. Comparison of combinational and sequential error rates for a deep submicron process. IEEE Transactions on Nuclear Science, 58(6):2719--2725, 2011.

[23]

D. Rossi, M. Omana, F. Toma, and C. Metra. Multiple transient faults in logic: an issue for next generation ics? In Proceedings of International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 352--360, 2005.

Digital Library

[24]

M. Fazeli, S. N. Ahmadian, S. G. Miremadi, H. Asadi, and M. B. Tahoori. Soft error rate estimation of digital circuits in the presence of multiple event transients. In Design, Automation Test in Europe Conference Exhibition, pages 1--6, 2011.

[25]

N. Miskov-Zivanov and D. Marculescu. Multiple transient faults in combinational and sequential circuits: A systematic approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(10):1614--1627, 2010.

Digital Library

[26]

C. Rusu, A. Bougerol, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, and R. Gaillard. Multiple event transient induced by nuclear reactions in cmos logic cells. In IEEE International On-Line Testing Symposium, pages 137--145, 2007.

Digital Library

[27]

R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, and M. J. Irwin. Seat-la: A soft error analysis tool for combinational logic. In Proceedings of the 19th International Conference on VLSI Design, pages --, 2006.

Digital Library

[28]

P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proceedings of the International Conference on Dependable Systems and Networks, pages 23--26, 2002.

Digital Library

[29]

M. Fazeli, S. G. Miremadi, H. Asadi, and S. N. Ahmadian. A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design. In Proceedings of the International Conference on Dependable Systems and Networks, pages 131--140, 2010.

[30]

R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert. Statistical fault injection: Quantified error and confidence. In Proceedings of Design, Automation and Test in Europe Conference, pages 502--506, 2009.

Digital Library

[31]

Synopsys Design Compiler. http://www.synopsys.com, 2012.

[32]

SOC Encounter. http://www.cadence.com, 2012.

Cited By

Bansal VMohamed ONethula S(2022)META: A Layout Based Tool to Estimate the Vulnerability of Digital Circuits to Multiple Event Transient2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9842148(450-454)Online publication date: 19-Jun-2022
https://doi.org/10.1109/NEWCAS52662.2022.9842148
Yakhchi MFazeli MAsghari S(2022)Silent Data Corruption Estimation and Mitigation Without Fault InjectionIEEE Canadian Journal of Electrical and Computer Engineering10.1109/ICJECE.2022.318904345:3(318-327)Online publication date: Oct-2023
https://doi.org/10.1109/ICJECE.2022.3189043
Zhao WChen WHe CChen RZhang FGuo XLu CShen C(2022)Heavy-ion and pulsed laser induced single-event double transients in nanometer inverter chainRadiation Effects and Defects in Solids10.1080/10420150.2022.2148250178:3-4(393-405)Online publication date: 22-Dec-2022
https://doi.org/10.1080/10420150.2022.2148250
Show More Cited By

Index Terms

A layout-based approach for multiple event transient analysis
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

An Enhanced Analytical Electrical Masking Model for Multiple Event Transients
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Due to the reducing transistor feature size, the susceptibility of modern circuits to radiation induced errors has increased. This, as a result, has increased the likelihood of multiple transients affecting a circuit. An important aspect when modeling ...
A fast and accurate hybrid fault injection platform for transient and permanent faults

Many ground-level and space systems require reliability testing before their deployment, since they are increasingly susceptible to transient and permanent faults. Such process must be accurate, controllable, generic, cheap, and fast. Even though fault ...
Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits

Recent radiation ground testing campaigns of digital designs have demonstrated that the probability for Single Event Transient (SET) propagation is increasing in advanced technologies. This paper presents a hierarchical reliability-aware synthesis ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

32
Total Citations
View Citations
237
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)1

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Bansal VMohamed ONethula S(2022)META: A Layout Based Tool to Estimate the Vulnerability of Digital Circuits to Multiple Event Transient2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9842148(450-454)Online publication date: 19-Jun-2022
https://doi.org/10.1109/NEWCAS52662.2022.9842148
Yakhchi MFazeli MAsghari S(2022)Silent Data Corruption Estimation and Mitigation Without Fault InjectionIEEE Canadian Journal of Electrical and Computer Engineering10.1109/ICJECE.2022.318904345:3(318-327)Online publication date: Oct-2023
https://doi.org/10.1109/ICJECE.2022.3189043
Zhao WChen WHe CChen RZhang FGuo XLu CShen C(2022)Heavy-ion and pulsed laser induced single-event double transients in nanometer inverter chainRadiation Effects and Defects in Solids10.1080/10420150.2022.2148250178:3-4(393-405)Online publication date: 22-Dec-2022
https://doi.org/10.1080/10420150.2022.2148250
Li YHan JZeng XTahoori M(2021)TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474176(88-93)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474176
Paturel JKritikakou ASentieys O(2020)Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI49217.2020.00067(328-333)Online publication date: Jul-2020
https://doi.org/10.1109/ISVLSI49217.2020.00067
Li YZeng XGao ZLin LTao JHan JCheng XTahoori MZeng X(2020)Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218696(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218696
Zhao WHe CChen WChen RCong PZhang FWang ZGuo XDing L(2019)Single-Event Double Transients in Inverter Chains Designed With Different Transistor WidthsIEEE Transactions on Nuclear Science10.1109/TNS.2019.289561066:7(1491-1499)Online publication date: Jul-2019
https://doi.org/10.1109/TNS.2019.2895610
Cao XXiao LLi JZhang RLiu SWang J(2019)A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442538:6(1109-1122)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2834425
Paliaroutis GTsoumanis PEvmorfopoulos NDimitriou GStamoulis G(2019)Multiple Transient Faults in Combinational Logic with Placement Considerations2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST.2019.8741538(1-4)Online publication date: May-2019
https://doi.org/10.1109/MOCAST.2019.8741538
Aketi SMekie JShah H(2018)Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2018.71(250-255)Online publication date: Jan-2018
https://doi.org/10.1109/VLSID.2018.71
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten