research-article

Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Authors:

Michael Kishinevsky,

Raid AyoubAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 114, Pages 1 - 7

https://doi.org/10.1145/2463209.2488874

Published: 29 May 2013 Publication History

Abstract

As the core count in processor chips grows, so do the on-die, shared resources such as on-chip communication fabric and shared cache, which are of paramount importance for chip performance and power. This paper presents a method for dynamic voltage/frequency scaling of networks-on-chip and last level caches in multicore processor designs, where the shared resources form a single voltage/frequency domain. Several new techniques for monitoring and control are developed, and validated through full system simulations on the PARSEC benchmarks. These techniques reduce energy-delay product by 56% compared to a state-of-the-art prior work.

References

[1]

Bienia, C., Kumar, S., Singh, J. P., and Li, K. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In PACT. 2008.

Digital Library

[2]

Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., et al. The gem5 simulator. ACM Computer Architecture News, 39(2):1--7, May 2011.

Digital Library

[3]

Bogdan, P., Marculescu, R., Jain, S., and Gavila, R. T. An optimal control approach to power management for multi-voltage and frequency islands multiprocessor platforms under highly variable workloads. In NOCS, pages 35--42. 2012.

Digital Library

[4]

Chen, X., Xu, Z., Kim, H., Gratz, P., et al. In-network monitoring and control policy for dvfs of cmp networks-on-chip and last level caches. In NOCS, pages 43--50. 2012.

Digital Library

[5]

Flautner, K., Kim, N. S., Martin, S., Blaauw, D., et al. Drowsy caches: simple techniques for reducing leakage power. In ISCA, pages 148--157. 2002.

Digital Library

[6]

Guang, L., Nigussie, E., Koskinen, L., and Tenhunen, H. Autonomous DVFS on supply islands for energy-constrained NoC communication. Lecture Notes in Computer Science: Architecture of Computing Systems, 5455/2009:183--194, 2009.

Digital Library

[7]

Kahng, A. B., Li, B., Peh, L. S., and Samadi, K. ORION 2.0: a power-area simulator for interconnection networks. TVLSI, 20(1):191--196, January 2012.

Digital Library

[8]

Kirolos, S. and Massoud, Y. Adaptive SRAM design for dynamic voltage scaling VLSI systems. In MWSCAS, pages 1297--1300. 2007.

[9]

Konstantakopoulos, T., Eastep, J., Psota, J., and Agarwal, A. Energy scalability of on-chip interconnection networks in multicore architectures. Technical report, MIT Computer Science and Artificial Intelligence Laboratory, November 2007.

[10]

Kowaliski, C. Gelsinger reveals details of Nehalem, Larrabee, Dunnington, 2008.

[11]

Kumar, R. and Hinton, G. A family of 45nm IA processors. In ISSCC, pages 58--59. 2009.

[12]

Liang, G. and Jantsch, A. Adaptive power management for the on-chip communication network. In Proeedings of the Euromicro Conference on Digital System Design. 2006.

Digital Library

[13]

Mishra, A. K., Das, R., Eachempati, S., Iyer, R., et al. A case for dynamic frequency tuning in on-chip networks. In MICRO, pages 292--303. 2009.

Digital Library

[14]

Muralimanohar, N., Balasubramonian, R., and Jouppi, N. P. CACTI 6.0: a tool to model large caches. Technical report, HP Laboratories, 2009.

[15]

Ogras, U. Y., Marculescu, R., and Marculescu, D. Variation-adaptive feedback control for networks-on-chip with multiple clock domains. In DAC, pages 614--619. 2008.

Digital Library

[16]

Rahimi, A., Salehi, M. E., Mohammadi, S., and Fakhraie, S. M. Low-energy GALS NoC with FIFO-monitoring dynamic voltage scaling. Microelectronics Journal, 42(6):889--896, June 2011.

Digital Library

[17]

Shang, L., Peh, L., and Jha, N. K. Power-efficient interconnection networks: dynamic voltage scaling with links. IEEE Computer Architecture Letters, 1(1), 2002.

Digital Library

[18]

Son, S. W., Malkowski, K., Chen, G., Kandemir, M., et al. Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse maxtrix applications. In IPDPS. 2006.

Digital Library

[19]

Wang, H., Peh, L. S., and Malik, S. Power-driven design of router microarchitectures in on-chip networks. In MICRO, pages 105--116. 2003.

Digital Library

Cited By

Fujita KNoguchi HFukuda HKaneko M(2023)Dynamic uncore frequency scaling based on performance events of Web applicationsProceedings of the 2023 8th International Conference on Cloud Computing and Internet of Things10.1145/3627345.3627350(31-37)Online publication date: 22-Sep-2023
https://dl.acm.org/doi/10.1145/3627345.3627350
Yao Y(2023)Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core ProcessorsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324476313:1(58-72)Online publication date: Mar-2023
https://doi.org/10.1109/JETCAS.2023.3244763
Wang SUsami K(2023)Thermal coupling analysis and improved dynamic temperature control algorithm for 3D-LSI2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)10.1109/ITC-CSCC58803.2023.10212704(1-6)Online publication date: 25-Jun-2023
https://doi.org/10.1109/ITC-CSCC58803.2023.10212704
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Dynamic voltage and frequency scaling for shared resources in multicore processor designs

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Cited By

Fujita KNoguchi HFukuda HKaneko M(2023)Dynamic uncore frequency scaling based on performance events of Web applicationsProceedings of the 2023 8th International Conference on Cloud Computing and Internet of Things10.1145/3627345.3627350(31-37)Online publication date: 22-Sep-2023
https://dl.acm.org/doi/10.1145/3627345.3627350
Yao Y(2023)Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core ProcessorsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324476313:1(58-72)Online publication date: Mar-2023
https://doi.org/10.1109/JETCAS.2023.3244763
Wang SUsami K(2023)Thermal coupling analysis and improved dynamic temperature control algorithm for 3D-LSI2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)10.1109/ITC-CSCC58803.2023.10212704(1-6)Online publication date: 25-Jun-2023
https://doi.org/10.1109/ITC-CSCC58803.2023.10212704
Nambinina ROnwuchekwa DObermaisser R(2023)Latency-Aware Frequency Scaling in Time-Triggered Network-on-Chip Architecture2023 7th International Conference on Computing Methodologies and Communication (ICCMC)10.1109/ICCMC56507.2023.10084313(1480-1488)Online publication date: 23-Feb-2023
https://doi.org/10.1109/ICCMC56507.2023.10084313
Zheng HLouri A(2022)Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip DesignIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.300349610:1(223-236)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TETC.2020.3003496
Wang SUsami K(2022)Thermal Transient Analysis and Dynamic Temperature Control Algorithm for 3-D Stacked Chips2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)10.1109/ITC-CSCC55581.2022.9895062(614-617)Online publication date: 5-Jul-2022
https://doi.org/10.1109/ITC-CSCC55581.2022.9895062
Reza M(2022)Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing SystemsIEEE Access10.1109/ACCESS.2022.318250010(65339-65354)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3182500
Yao YLu Z(2020)Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFSIEEE Transactions on Computers10.1109/TC.2019.294980769:3(410-426)Online publication date: 1-Mar-2020
https://doi.org/10.1109/TC.2019.2949807
Clark MChen YKaranth AMa BLouri A(2020)DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00011(1-11)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00011
Zheng HLouri A(2019)An Energy-Efficient Network-on-Chip Design using Reinforcement LearningProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317768(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317768
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