research-article

Reconfigurable pipelined coprocessor for multi-mode communication transmission

Authors:

Jude Angelo Ambrose,

Sri ParameswaranAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 134, Pages 1 - 8

https://doi.org/10.1145/2463209.2488899

Published: 29 May 2013 Publication History

Abstract

The need to integrate multiple wireless communication protocols into a single low-cost, low-power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents a novel application specific platform for integrating multiple wireless communication transmission baseband protocols in a pipelined coprocessor, which can be programmed to support various baseband protocols. This coprocessor can dynamically select the suitable pipeline stages for each baseband protocol. Moreover, each carefully designed stage is able to perform a certain signal processing function in a reconfigurable fashion. The proposed platform is flexible (compared to ASICs) and is suitable for mobile applications (compared to FPGAs and processors). The area footprint of the coprocessor is smaller than an ASIC or FPGA implementation of multiple individual protocols, while the overhead of throughput is 34% worse than ASICs and 32% better than FPGAs. The power consumption is 2.7X worse than ASICs but 40X better than FPGAs on average. The proposed platform outperforms processor implementation in all area, throughput and power consumption. Moreover, fast protocol switching is supported. Wireless LAN (WLAN) 802.11a, WLAN 802.11b and Ultra Wide Band (UWB) transmission circuits are developed and mapped to the pipelined coprocessor to prove the efficacy of our proposal.

References

[1]

D. A. Reed, J. R. Larus, and D. Gannon, "Imagining the future: Thoughts on computing," IEEE Computer, vol. 45, no. 1, pp. 25--30, 2012.

Digital Library

[2]

"Bcm4330 product brief." Available at: www.broadcom.com.

[3]

L. S. Nagurney, "Software defined radio in the electrical and computer engineering curriculum," in Proceedings of the 39th IEEE international conference on Frontiers in education conference, FIE'09, 2009.

Digital Library

[4]

N. Himanshu Shekhar, C. B. Mahto, "FPGA Implementation of Tunable FFT For SDR Receiver," in International Journal of Computer Science and Network Security, pp. 186--190, 2009.

[5]

Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, and K. Flautner, "Soda: A high-performance dsp architecture for software-defined radio," IEEE Micro, vol. 27, pp. 114--123, 2007.

Digital Library

[6]

A. Duller, D. Towner, G. Panesar, A. Gray, and W. Robbins, "picoArray Technology: The Tool's Story," in DATE, 2005.

Digital Library

[7]

M. I. Taj, O. Hammami, and M. Akil, "SDR waveform components implementation on single FPGA multiprocessor platform," in ICECS, pp. 790--793, Dec. 2010.

[8]

"Multiband ofdm physical layer specification," 2005. Available at: http://www.wimedia.org/.

[9]

"Official ieee 802.11 working group project timelines," 2011. Available at: http://www.ieee802.org/11/Reports/802.11_Timelines.htm.

[10]

L. Tang, J. Peddersen, and S. Parameswaran, "A rapid methodology for multi-mode communication circuit generation," in Proceedings of the 2012 25th International Conference on VLSI Design, 2012.

Digital Library

[11]

P. Coulton and D. Carline, "An SDR inspired design for the FPGA implementation of 802.11a baseband system," in IEEE Symposium on Consumer Electronics, 2004.

[12]

M. Cummings and S. Haruyama, "FPGA in the Software Radio," IEEE Communications Magazine, vol. 37, pp. 108--112, 1999.

Digital Library

[13]

C. Dick and F. Harris, "Configurable logic for digital communications it's about time," in Signals, Systems, and Computers, Conference, 1999.

[14]

I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," in FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, (New York, NY, USA), pp. 21--30, ACM, 2006.

Digital Library

[15]

H. Karimi, N. Anderson, and P. McAndrew, "Digital signal processing aspects of software definable radios," in IEE Colloquium on Adaptable and Multistandard Mobile Radio Terminals, 1998.

[16]

D. Pulley and R. Baines, "Software defined baseband processing for 3G base stations," in 4th International Conference on 3G Mobile Communication Technologie, 2003.

[17]

N. Moreano, E. Borin, C. D. Souza, and G. Araujo, "Efficient datapath merging for partially reconfigurable architectures," in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 969--980, 2005.

Digital Library

[18]

B. Krill and A. Amira, "Efficient reconfigurable architectures of generic cyclic convolution," in B. Krill, A. Amira, 2011.

[19]

C. R. Sanchez-Ortiz, R. Parra-Michel, and M. Guzman-Renteria, "Design and implementation of a multi-standard interleaver for 802.11a, 802.11n, 802.16e & dvb standards," Reconfigurable Computing and FPGAs, International Conference on, vol. 0, pp. 379--384, 2008.

Digital Library

[20]

B. K. Upadhyaya and S. K. Sanyal, "Design of a novel fsm based reconfigurable multimode interleaver for wlan application," in International Conference on Devices and Communications, 2011.

[21]

K. Smitha, A. P. Vinod, and R. Mahesh, "Reconfigurable area and power efficient i-q mapper for adaptive modulation," in International Midwest Symposium on Circuits and Systems, 2011.

[22]

J.-C. Lin, C. Yu, M.-H. Yen, P.-A. Hsiung, S.-J. Chen, and Y. H. Hu, "Parallel implementation of convolution encoder for software defined radio on dsp architecture," in ICSAMOS, pp. 180--186, 2009.

Digital Library

[23]

L. Tang, J. A. Ambrose, and S. Parameswaran, "Variable increment step based reconfigurable interleaver for multimode communication application," in ISCAS'13: The IEEE International Symposium on Circuits and Systems, 2013.

[24]

L. Tang, J. A. Ambrose, and S. Parameswaran, "MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping," in Proceedings of the 2013 26th International Conference on VLSI Design, 2013.

Digital Library

[25]

"Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications," 2011. Available at: http://standards.ieee.org/.

[26]

J. Proakis, Digital communications. McGraw-Hill series in electrical and computer engineering, McGraw-Hill, 2001.

[27]

"ASIP Solutions ASIPMeister." Available at: http://www.asip-solutions.com/en/asip_meister.html/.

[28]

"Mathworks matlab." Available at: http://www.mathworks.com/.

[29]

"Transistor count." Available at: http://en.wikipedia.org/wiki/Transistor_count.

[30]

"Xtensa Processor." Tensilica Inc. (http://www.tensilica.com).

Cited By

Al-Doori QAlani O(2018)Utilizing Frequency Changing in Communication Systems to Reduce Power in CRC Circuits2018 Third Scientific Conference of Electrical Engineering (SCEE)10.1109/SCEE.2018.8684028(258-290)Online publication date: Dec-2018
https://doi.org/10.1109/SCEE.2018.8684028
Tabkhi HBushey RSchirner G(2018)Function-Level Processor (FLP)Journal of Signal Processing Systems10.1007/s11265-015-1058-585:3(287-306)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-015-1058-5
Tabkhi HBushey RSchirner G(2014)Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2014.6868646(121-130)Online publication date: Jun-2014
https://doi.org/10.1109/ASAP.2014.6868646

Index Terms

Reconfigurable pipelined coprocessor for multi-mode communication transmission
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits

Recommendations

A multi-mode video-stream processor with cyclically reconfigurable architecture
CF '08: Proceedings of the 5th conference on Computing frontiers

This paper presents an approach for development of cost-effective hardware platform for video/image processing. The approach utilizes the SRAM based reconfigurable logic devices (FPGAs) and, their capability of run-time temporal partitioning of logic ...
Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational ...
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs

FPGAs are widely used in today's embedded systems design due to their low cost, high performance, and reconfigurability. Partially RunTime-Reconfigurable (PRTR) FPGAs, such as Virtex-2 Pro and Virtex-4 from Xilinx, allow part of the FPGA area to be ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
123
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Al-Doori QAlani O(2018)Utilizing Frequency Changing in Communication Systems to Reduce Power in CRC Circuits2018 Third Scientific Conference of Electrical Engineering (SCEE)10.1109/SCEE.2018.8684028(258-290)Online publication date: Dec-2018
https://doi.org/10.1109/SCEE.2018.8684028
Tabkhi HBushey RSchirner G(2018)Function-Level Processor (FLP)Journal of Signal Processing Systems10.1007/s11265-015-1058-585:3(287-306)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-015-1058-5
Tabkhi HBushey RSchirner G(2014)Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2014.6868646(121-130)Online publication date: Jun-2014
https://doi.org/10.1109/ASAP.2014.6868646

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten