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Time-domain segmentation based massively parallel simulation for ADCs

Authors:

Zuochang Ye,

Bichen Wu,

Song Han,

Yang LiAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 139, Pages 1 - 6

https://doi.org/10.1145/2463209.2488905

Published: 29 May 2013 Publication History

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Abstract

The great availability of massively parallel computing platforms gives rise a question to the EDA industry--how can this be really helping the productivity of circuit designs. Scalability of traditional parallel methods have shown to be limited as the computational resources keep increasing. In this paper we propose a time-domain segmentation method for massively parallel transistor-level simulation for short-memory circuits. SNDR simulation for ADCs is selected as the application as ADCs are typical short-memory circuits and the SNDR simulation is very time consuming. Experiments with realistic Flash and SAR ADCs demonstrate 64x-78x speed-ups with 100 CPU cores. With minor, yet important modifications, the proposed method can even be applied to simulation of Σ-Δ modulator, which does not satisfy the short-memory condition due to the presence of integrator, and 52x speed-up is observed with 100 CPU cores. The implementation of the proposed method is extremely simple and no modification to simulator is needed.

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Cited By

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Zhou JYang WDong FLin SCai QLi K(2024)NUMA-aware parallel sparse LU factorization for SPICE-based circuit simulators on ARM multi-core processorsThe International Journal of High Performance Computing Applications10.1177/10943420241241491Online publication date: 23-Oct-2024
https://doi.org/10.1177/10943420241241491
Chen XWang YYang HChen XWang YYang H(2017)Related WorkParallel Sparse Direct Solver for Integrated Circuit Simulation10.1007/978-3-319-53429-9_2(13-41)Online publication date: 12-Feb-2017
https://doi.org/10.1007/978-3-319-53429-9_2
Chen XWang YYang HChen XWang YYang H(2017)IntroductionParallel Sparse Direct Solver for Integrated Circuit Simulation10.1007/978-3-319-53429-9_1(1-12)Online publication date: 12-Feb-2017
https://doi.org/10.1007/978-3-319-53429-9_1
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Time-domain segmentation based massively parallel simulation for ADCs
1. Hardware

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Published In

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 29 May 2013

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Zhou JYang WDong FLin SCai QLi K(2024)NUMA-aware parallel sparse LU factorization for SPICE-based circuit simulators on ARM multi-core processorsThe International Journal of High Performance Computing Applications10.1177/10943420241241491Online publication date: 23-Oct-2024
https://doi.org/10.1177/10943420241241491
Chen XWang YYang HChen XWang YYang H(2017)Related WorkParallel Sparse Direct Solver for Integrated Circuit Simulation10.1007/978-3-319-53429-9_2(13-41)Online publication date: 12-Feb-2017
https://doi.org/10.1007/978-3-319-53429-9_2
Chen XWang YYang HChen XWang YYang H(2017)IntroductionParallel Sparse Direct Solver for Integrated Circuit Simulation10.1007/978-3-319-53429-9_1(1-12)Online publication date: 12-Feb-2017
https://doi.org/10.1007/978-3-319-53429-9_1
Nandi PTalukdar HKumar DKatakwar A(2016)A Novel Approach to Design SAR-ADCIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.247437935:3(346-356)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2474379
Serhan AVelayudhan VAniculaesei V(2014)Integration of free SPICE Simulator into the Cadence EnvironmentMELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference10.1109/MELCON.2014.6820577(458-461)Online publication date: Apr-2014
https://doi.org/10.1109/MELCON.2014.6820577

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65-nm CMOS Voltage-to-Time Converter for 5-GS/s Time-Based ADCs

A new design methodology for voltage-to-frequency converters (VFCs) circuits suitable for time-based analog-to-digital converters (T-ADCs)

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

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