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Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power

Published: 29 May 2013 Publication History

Abstract

We propose a path to achieve an ambitious target that has never been tried before: a terabyte of on-chip memory for petabit/second of bandwidth with < 5W of power. Conventional methodology of on-chip memory design is bottom up where the choice of bitcell topology and associated peripherals are predetermined. The resulting memory is sub-optimal and often suffers from high power and poor bandwidth. We approach this problem from top down where the capacity, bandwidth and power specifications guide the choice of bitcell. Our evaluation shows that domain wall memory (DWM) can be a potential technology that can meet TB capacity and Pb/s bandwidth with shoestring power budget.

References

[1]
Asanovic, Krste, et al, Technical Report, 2006.
[2]
Rogers, B M., et al, SIGARCH, 2009.
[3]
Kalla, R et al, Micro, 2010.
[4]
Wang, Y. et al, JSSC, 2010.
[5]
http://www.anandtech.com/show/5771/the-intel-ivy-bridge-core-i7-3770k-review/3.
[6]
E. Karl et al., ISSCC 2012.
[7]
Fayé A Briggs, ICAF, 2011.
[8]
M. H. Kryder et al, 2009.
[9]
Wordeman, M., et al, ISSCC, 2012.
[10]
Parkin, S. et al, Science, 2008.
[11]
http://news.cnet.com/8301-21546_3-57400009-10253464/seagate-reaches-1tb-per-square-inch-hard-drive-to-reach-60tb-capacity/.
[12]
http://hybridmemorycube.org/files/SiteDownloads/20120710_HPCWire_HMCAnglesforExascale.pdf.
[13]
http://www.realworldtech.com/terabyte-intiative/1/.
[14]
http://www.asu.edu/~ptm.
[15]
A. J. Annunziata et al, IEDM 2011.
[16]
R. Venkatesan et al, ISLPED, 2012.
[17]
Thomas, L., et al, IEDM, 2011.
[18]
Sekiguchi, T., et al, JSSC 2011.

Cited By

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  • (2016)A Survey of Techniques for Architecting Processor Components Using Domain-Wall MemoryACM Journal on Emerging Technologies in Computing Systems10.1145/299455013:2(1-25)Online publication date: 3-Nov-2016
  • (2016)Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-EfficiencyProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934602(332-337)Online publication date: 8-Aug-2016
  • (2016)Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.243728324:3(944-953)Online publication date: 1-Mar-2016
  • Show More Cited By

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  1. Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power

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      cover image ACM Conferences
      DAC '13: Proceedings of the 50th Annual Design Automation Conference
      May 2013
      1285 pages
      ISBN:9781450320719
      DOI:10.1145/2463209
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 29 May 2013

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      Author Tags

      1. domain wall memory
      2. high density
      3. low-power memory

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      View all
      • (2016)A Survey of Techniques for Architecting Processor Components Using Domain-Wall MemoryACM Journal on Emerging Technologies in Computing Systems10.1145/299455013:2(1-25)Online publication date: 3-Nov-2016
      • (2016)Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-EfficiencyProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934602(332-337)Online publication date: 8-Aug-2016
      • (2016)Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.243728324:3(944-953)Online publication date: 1-Mar-2016
      • (2016)Overview of Circuits, Systems, and Applications of SpintronicsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.26013106:3(265-278)Online publication date: Sep-2016
      • (2015)Optimizing data placement for reducing shift operations on domain wall memoriesProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744883(1-6)Online publication date: 7-Jun-2015
      • (2015)Domain wall memory based digital signal processors for area and energy-efficiencyProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744825(1-6)Online publication date: 7-Jun-2015
      • (2015)Domain Wall Memory-Layout, Circuit and Synergistic SystemsIEEE Transactions on Nanotechnology10.1109/TNANO.2015.239118514:2(282-291)Online publication date: 6-Mar-2015
      • (2015)Domain Wall Magnets for Embedded Memory and Hardware SecurityIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2015.23982325:1(40-50)Online publication date: Mar-2015
      • (2014)Synergistic circuit and system design for energy-efficient and robust domain wall cachesProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627643(195-200)Online publication date: 11-Aug-2014
      • (2014)Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded MemoryProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593161(1-6)Online publication date: 1-Jun-2014

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