research-article

Routability-driven placement for hierarchical mixed-size circuit designs

Authors:

Chau-Chin Huang,

Tung-Chieh Chen,

Yao-Wen ChangAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 151, Pages 1 - 6

https://doi.org/10.1145/2463209.2488921

Published: 29 May 2013 Publication History

Abstract

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wire-length) and the best overall score (by additionally considering running time).

References

[1]

ICCAD 2012 Placement Contest. http://cadcontest.cs.nctu.edu.tw/CAD-contest-at-ICCAD2012/.

[2]

U. Brenner, M. Struzyna, and J. Vygen. BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms. IEEE Tran. on CAD, 27(9):1607--1620, September 2008.

Digital Library

[3]

T. F. Chan, J. Cong, T. Kong, and J. R. Shinnerl. Multilevel optimization for large-scale circuit placement. In Proc. of ICCAD, pages 171--176, 2000.

Digital Library

[4]

Y.-W. Chang, Z.-W. Jiang, and T.-C. Chen. Essential issues in analytical placement algorithms. IPSJ Tran. on SLDM, 2:145--166, August 2009.

[5]

T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Tran. on CAD, 27(7):1228--1240, July 2008.

Digital Library

[6]

S. Chou, M.-K. Hsu, and Y.-W. Chang. Structure-aware placement for datapath-intensive circuit designs. In Proc. of DAC, pages 762--767, 2012.

Digital Library

[7]

Y.-L. Chuang, G.-J. Nam, C. J. Alpert, Y.-W. Chang, J. Roy, and N. Viswanathan. Design-hierarchy aware mixed-size placement for routability optimization. In Proc. of ICCAD, pages 663--668, 2010.

Digital Library

[8]

R. C. Gonzales and R. E. Woods. Digital Image Processing. Addison-Wesley, 1992.

Digital Library

[9]

X. He, T. Huang, L. Xiao, H. Tian, G. Cui, and E. F. Y. Young. Ripple: An effective routability-driven placer by iterative cell movement. In Proc. of ICCAD, pages 74--79, 2011.

Digital Library

[10]

D. Hill. US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design. 2002.

[11]

M.-K. Hsu, Y.-W. Chang, and V. Balabanov. TSV-aware analytical placement for 3D IC designs. In Proc. of DAC, pages 664--669, 2011.

Digital Library

[12]

M.-K. Hsu, S. Chou, T.-H. Lin, and Y.-W. Chang. Routability-driven analytical placement for mixed-size circuit designs. In Proc. of ICCAD, pages 80--84, 2011.

Digital Library

[13]

J. Hu, J. A. Roy, and I. L. Markov. Completing high-quality global routes. In Proc. of ISPD, pages 35--41, 2010.

Digital Library

[14]

Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang. Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. In Proc. of DAC, pages 167--172, 2008.

Digital Library

[15]

M.-C. Kim, J. Hu, D.-J. Lee, and I. L. Markov. A SimPLR method for routability-driven placement. In Proc. of ICCAD, pages 67--73, 2011.

Digital Library

[16]

C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H. Madden. Routability-driven placement and white space allocation. In Proc. of ICCAD, pages 394--401, 2004.

Digital Library

[17]

W.-H. Liu, W.-C. Kao, Y.-L. Li, and K.-Y. Chao. Multi-threaded collision-aware global routing with bounded-length maze routing. In Proc. of DAC, pages 200--205, 2010.

Digital Library

[18]

J. A. Roy, J. F. Lu, and I. L. Markov. Seeing the forest and the trees: Steiner wirelength optimization in placement. IEEE Tran. on CAD, 26(4):632--644, April 2007.

Digital Library

[19]

J. A. Roy, N. Viswanathan, G.-J. Nam, C. J. Alpert, and I. L. Markov. CRISP: Congestion reduction by iterated spreading during placement. In Proc. of ICCAD, pages 357--362, 2009.

Digital Library

[20]

P. Spindler and F. M. Johannes. Fast and accurate routing demand estimation for efficient routability-driven placement. In Proc. of DATE, pages 1226--1231, 2007.

Digital Library

[21]

K. Tsota, C. Koh, and V. Balakrishnan. Guiding global placement with wire density. In Proc. of ICCAD, pages 212--217, 2008.

Digital Library

[22]

N. Viswanathan, C. Alpert, C. Sze, Z. Li, and Y. Wei. ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. In Proc. of ICCAD, pages 345--348, 2012.

Digital Library

[23]

X. Yang, B.-K. Choi, and M. Sarrafzadeh. Routability-driven white space allocation for fixed-die standard-cell placement. In Proc. of ISPD, pages 410--419, 2002.

Digital Library

Cited By

Kahng AVaradarajan RWang Z(2024) Hier-RTLMP : A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334628443:5(1552-1565)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3346284
Yu HHuang SRen L(2024)Research on Methods for Very Large Scale Integration Track Assignment RoutingMATEC Web of Conferences10.1051/matecconf/202439900015399(00015)Online publication date: 24-Jun-2024
https://doi.org/10.1051/matecconf/202439900015
Kahng AVaradarajan RWang ZBehjat LYang S(2022)RTL-MPProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3506731(3-11)Online publication date: 13-Apr-2022
https://dl.acm.org/doi/10.1145/3505170.3506731
Show More Cited By

Index Terms

Routability-driven placement for hierarchical mixed-size circuit designs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs
DAC '08: Proceedings of the 45th annual Design Automation Conference

Routability is a challenging cost metric for modern large-scale mixed-size placement. Most existing routability-driven placement algorithms apply whitespace allocation to relieve the routing congestion. Nevertheless, we observe that whitespace ...
Routability-Driven Blockage-Aware Macro Placement
DAC '14: Proceedings of the 51st Annual Design Automation Conference

We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CP-trees can flexibly pack movable macros toward corners or pre-placed macros along chip boundaries circularly to optimize macro ...
Routability driven white space allocation for fixed-die standard-cell placement
ISPD '02: Proceedings of the 2002 international symposium on Physical design

The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

34
Total Citations
View Citations
431
Total Downloads

Downloads (Last 12 months)16
Downloads (Last 6 weeks)2

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Kahng AVaradarajan RWang Z(2024) Hier-RTLMP : A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334628443:5(1552-1565)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3346284
Yu HHuang SRen L(2024)Research on Methods for Very Large Scale Integration Track Assignment RoutingMATEC Web of Conferences10.1051/matecconf/202439900015399(00015)Online publication date: 24-Jun-2024
https://doi.org/10.1051/matecconf/202439900015
Kahng AVaradarajan RWang ZBehjat LYang S(2022)RTL-MPProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3506731(3-11)Online publication date: 13-Apr-2022
https://dl.acm.org/doi/10.1145/3505170.3506731
Jing YYang LZhuang ZLiu GHuang XLiu WWang T(2022)SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939624(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939624
Liu GZhang XGuo WHuang XLiu WChao KWang T(2022)Timing-Aware Layer Assignment for Advanced Process Technologies Considering via PillarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310029641:6(1957-1970)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3100296
Vidal-Obiols ACortadella JPetit JGalceran-Oms MMartorell F(2021)Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical MethodsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.304772440:12(2542-2555)Online publication date: Dec-2021
https://doi.org/10.1109/TCAD.2020.3047724
Vidal-Obiols ACortadella JPetit JGalceran-Oms MMartorell F(2019)RTL-Aware Dataflow-Driven Macro Placement2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714812(186-191)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8714812
Liu GZhuang ZGuo WWang THomayoun HTaskin BMohsenin TZhao W(2019)RDTAProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318026(315-318)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318026
Huang CLee HLin BYang SChang CChen SChang YChen TBustany I(2018)NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266537:3(669-681)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2712665
Chen SChang YChen TParameswaran S(2017)An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designsProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199766(496-503)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199766
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten