skip to main content
10.1145/2463209.2488928acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

DMR3D: dynamic memory relocation in 3D multicore systems

Published: 29 May 2013 Publication History

Abstract

Three-dimensional Multicore Systems present unique opportunities for proximity driven data placement in the memory banks. Coupled with distributed memory controllers, a design trend seen in recent systems, we propose a Dynamic Memory Relocator for 3D Multicores (DMR3D) to dynamically migrate physical pages among different memory controllers. Our proposed technique avoids long interconnect delays, and increases the use of vertical interconnect, thereby substantially reducing memory access latency and communication energy. Our techniques show 30% and 25% average performance and communication energy improvement on real world applications.

References

[1]
{SR1} Chang, J., and Sohi, G. S. Cooperative cache partitioning for chip multiprocessors. In International Conference on Supercomputing (2007).
[2]
{SR2} Muralimanohar and others CACTI 6.0: A tool to model large caches. University of Utah, School of Computing, Technical Report (2007).

Cited By

View all
  • (2014)Scenario-aware data placement and memory area allocation for multi-processor system-on-chips with reconfigurable 3D-stacked SRAMsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617069(1-6)Online publication date: 24-Mar-2014

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '13: Proceedings of the 50th Annual Design Automation Conference
May 2013
1285 pages
ISBN:9781450320719
DOI:10.1145/2463209
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

In-Cooperation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Conference

DAC '13
Sponsor:

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 14 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2014)Scenario-aware data placement and memory area allocation for multi-processor system-on-chips with reconfigurable 3D-stacked SRAMsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617069(1-6)Online publication date: 24-Mar-2014

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media