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Power gating applied to MP-SoCs for standby-mode power management

Published: 29 May 2013 Publication History

Abstract

Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional processor cores support both general purpose and graphics optimized processing in mobile SoCs, but the number of cores that may be simultaneously active is typically restricted for both battery life and thermal package limits. Power gating is the primary approach to cutting the leakage power for inactive blocks, while state retention and standby voltage scaling can be valuable enhancements for improving energy and latency costs for such leakage mitigation schemes. This paper describes work on techniques that look promising to build on current multi-voltage EDA tools and power intent, without the costs of resorting to full-custom design techniques.

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Cited By

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  • (2017)A scan-chain based state retention methodology for IoT processors operating on intermittent energyProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130655(1171-1176)Online publication date: 27-Mar-2017
  • (2017)A scan-chain based state retention methodology for IoT processors operating on intermittent energyDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927166(1171-1176)Online publication date: Mar-2017

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cover image ACM Conferences
DAC '13: Proceedings of the 50th Annual Design Automation Conference
May 2013
1285 pages
ISBN:9781450320719
DOI:10.1145/2463209
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 29 May 2013

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Author Tags

  1. IP-deployment
  2. central processor unit (CPU)
  3. dynamic voltage and frequency scaling (DVFS)
  4. electronic design automation (EDA)
  5. energy-efficiency
  6. implementation IP (IIP)
  7. intellectual property (IP)
  8. logical IP (LIP)
  9. low-power
  10. multi-threshold CMOS (MTCMOS)
  11. multi-voltage (MV)
  12. physical IP (PIP)
  13. power intent
  14. power-gating (PG)
  15. standard-cell
  16. state-retention (SR)
  17. system-on-chip (SoC)

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Cited By

View all
  • (2017)A scan-chain based state retention methodology for IoT processors operating on intermittent energyProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130655(1171-1176)Online publication date: 27-Mar-2017
  • (2017)A scan-chain based state retention methodology for IoT processors operating on intermittent energyDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927166(1171-1176)Online publication date: Mar-2017

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