research-article

Power management and delivery for high-performance microprocessors

Authors:

Tanay Karnik,

Mondira (Mandy) Pant,

Shekhar BorkarAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 159, Pages 1 - 3

https://doi.org/10.1145/2463209.2488931

Published: 29 May 2013 Publication History

Get Access

Abstract

This paper provides an introduction to advanced power management and delivery techniques that have been employed in leading microprocessor designs. The techniques need multiple voltage rails supplied by independent voltage regulators. We provide justification for near-load regulators and explain the practical challenges associated with the regulator integration.

References

[1]

Reidlinger, R. J., et al. 2011. A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. IEEE ISSCC. (Feb. 2011), 84--86. DOI=10.1109/ISSCC.2011.5746230.

Crossref

Google Scholar

[2]

Yuffe, M., et al. 2012. A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor. IEEE JSSC. 47, 1. (Jan. 2012), 194--205. DOI=10.1109/JSSC.2011.2167814.

Crossref

Google Scholar

[3]

Karnik, T., 2012. Power Management using Integrated Voltage Regulators. Tutorial T6. IEEE ISSCC. (Feb. 2012).

Google Scholar

[4]

Schrom, G., et al. 2004. Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. IEEE ISLPED. (Aug. 2004), 263--268. DOI=10.1109/LPE.2004.1349348.

Digital Library

Google Scholar

[5]

Hazucha, P., et al. 2005. Area-efficient linear regulator with ultra-fast load regulation. IEEE JSSC. 40, 4. (April. 2005), 933--940. DOI=10.1109/JSSC.2004.842831.

Crossref

Google Scholar

[6]

Le, H. P., et al. 2013. A Sub-ns Response Fully Integrated Battery-Connected Switched-Capacitor Voltage Regulator Delivering 0.19W/mm2 at 73% Efficiency. IEEE ISSCC (Feb. 2013), 371--372.

Google Scholar

[7]

Schrom, G., et al. 2004. A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control. IEEE PESC. 35. (Jun. 2004), 4702--4707.

Google Scholar

[8]

Gardner, D. S., et al. 2009. Review of On-Chip Inductor Structures With Magnetic Films. IEEE TMAG. 45, 10. (Oct. 2009), 4760--4766.

Google Scholar

Cited By

View all

Roth AZhou CWong MSoenen EHuang TRanucci PHsu YLin HKuo CWang MYang SChu JYeh TTing KLoke ARusu SChen MLee FZhang KKalnitsky A(2020)Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors using Integrated Passive Device and In-Package Voltage Regulator2020 IEEE Symposium on VLSI Technology10.1109/VLSITechnology18217.2020.9265105(1-2)Online publication date: Jun-2020
https://doi.org/10.1109/VLSITechnology18217.2020.9265105
Kalyanam VMahurin ESpence MAbraham J(2020)Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor2020 IEEE International Test Conference (ITC)10.1109/ITC44778.2020.9325271(1-10)Online publication date: 1-Nov-2020
https://doi.org/10.1109/ITC44778.2020.9325271
Park YSalman E(2020)High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180776(1-5)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180776
Show More Cited By

Index Terms

Power management and delivery for high-performance microprocessors
1. Hardware
  1. Integrated circuits

Recommendations

Cost-effective power delivery to support per-core voltage domains for power-constrained processors
DAC '12: Proceedings of the 49th Annual Design Automation Conference

Per-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have one chip-wide voltage domain because splitting the voltage domain into per-core voltage domains and powering them with multiple off-...
Power delivery for high performance microprocessors
ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

Robust power delivery is considered one the prime challenges in chip design today. As the frequency and complexity of microprocessors increase, the static and dynamic components of power supply noise increase. However, keeping with Moore's law, the ...
Managing power constraints in a single-core scenario through power tokens

Current microprocessors face constant thermal and power-related problems during their everyday use, usually solved by applying a power budget to the processor/core. Dynamic voltage and frequency scaling (DVFS) has been an effective technique that ...

Comments

Information & Contributors

Information

Published In

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
318
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Roth AZhou CWong MSoenen EHuang TRanucci PHsu YLin HKuo CWang MYang SChu JYeh TTing KLoke ARusu SChen MLee FZhang KKalnitsky A(2020)Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors using Integrated Passive Device and In-Package Voltage Regulator2020 IEEE Symposium on VLSI Technology10.1109/VLSITechnology18217.2020.9265105(1-2)Online publication date: Jun-2020
https://doi.org/10.1109/VLSITechnology18217.2020.9265105
Kalyanam VMahurin ESpence MAbraham J(2020)Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor2020 IEEE International Test Conference (ITC)10.1109/ITC44778.2020.9325271(1-10)Online publication date: 1-Nov-2020
https://doi.org/10.1109/ITC44778.2020.9325271
Park YSalman E(2020)High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180776(1-5)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180776
Sadat SCanbolat MKöse S(2018)Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power GridACM Transactions on Design Automation of Electronic Systems10.1145/317787723:4(1-15)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3177877
Najafi ARudell JSathe V(2016)Regenerative BreakingProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934621(94-99)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934621
Mantovani PCota ETien KPilato CDi Guglielmo GShepard KCarloni L(2016)An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systemsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897984(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2897984
Inadomi YPatki TInoue KAoyagi MRountree BSchulz MLowenthal DWada YFukazawa KUeda MKondo MMiyoshi IKern JVetter J(2015)Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputingProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/2807591.2807638(1-12)Online publication date: 15-Nov-2015
https://dl.acm.org/doi/10.1145/2807591.2807638

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Cost-effective power delivery to support per-core voltage domains for power-constrained processors

Power delivery for high performance microprocessors

Managing power constraints in a single-core scenario through power tokens

Comments

Information

Published In

Sponsors

In-Cooperation

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations