research-article

Flexible on-chip power delivery for energy efficient heterogeneous systems

Authors:

Benton H. Calhoun,

Kyle CraigAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 160, Pages 1 - 6

https://doi.org/10.1145/2463209.2488932

Published: 29 May 2013 Publication History

Abstract

Heterogeneous systems-on-chip pose a challenge for power delivery given the variety of needs for different components. In this paper, we describe recent work that leverages power switches and conventional EDA toolflows to implement a set of power delivery schemes that provide a flexible, adaptable range of options for power management of SoCs for which energy efficiency is important. We first present an enhanced dynamic voltage scaling (DVS) scheme that uses power switches to provide rapid changes in the energy-speed operating point to match workloads at a component level. To demonstrate this approach, we describe a data flow processor chip in 90nm CMOS that supports flexible operation from 0.25V with super high energy efficiency up to GHz speeds at 1.2V. This chip shows that our low overhead method to scale energy consumption with the performance requirement supports both high performance and ultra low energy (>10X reduction in energy per operation) in the same circuit. We discuss power switch design for this scheme and investigate strategies for optimizing power switches for different operating modes. Finally, we show how segmented power switches offer several advantages for flexibly managing leakage and for modulating local voltages with low overhead.

References

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Digital Library

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Y. Shakhsheer, S. Khanna, K. Craig, S. Arrabi, J. Lach, and B. H. Calhoun, "A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V," CICC, 2011.

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K. Craig, Y. Shakhsheer, and B. H. Calhoun, "Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation," ISLPED, 2012.

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K. Craig, Y. Shakhsheer, S. Khanna, S. Arrabi, J. Lach, B. H. Calhoun, and S. Kosonocky, "A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs," ISLPED, 2012.

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Cited By

Ye QWang XGong JRu SSu D(2017)IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel MethodAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0203912:3(711-721)Online publication date: Jun-2017
https://doi.org/10.25046/aj020391
Pundir ASharma O(2017)Fault tolerant reconfigurable hardware design using BIST on SRAM: A review2017 International Conference on Intelligent Computing and Control (I2C2)10.1109/I2C2.2017.8321907(1-16)Online publication date: Jun-2017
https://doi.org/10.1109/I2C2.2017.8321907
Jia TFan YJoseph RGu J(2016)Exploration of associative power management with instruction governed operation for ultra-low power designProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898021(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898021
Show More Cited By

Index Terms

Flexible on-chip power delivery for energy efficient heterogeneous systems
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. Hardware

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

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New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Cited By

Ye QWang XGong JRu SSu D(2017)IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel MethodAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0203912:3(711-721)Online publication date: Jun-2017
https://doi.org/10.25046/aj020391
Pundir ASharma O(2017)Fault tolerant reconfigurable hardware design using BIST on SRAM: A review2017 International Conference on Intelligent Computing and Control (I2C2)10.1109/I2C2.2017.8321907(1-16)Online publication date: Jun-2017
https://doi.org/10.1109/I2C2.2017.8321907
Jia TFan YJoseph RGu J(2016)Exploration of associative power management with instruction governed operation for ultra-low power designProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898021(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898021
Mercati PPaterna FBartolini ABenini LRosing T(2014)Dynamic variability management in mobile multicore processors under lifetime constraints2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974718(448-455)Online publication date: Oct-2014
https://doi.org/10.1109/ICCD.2014.6974718

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