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DuraCache: a durable SSD cache using MLC NAND flash

Published: 29 May 2013 Publication History

Abstract

Adopting SSDs as caches for HDD arrays has gained popularity in datacenters because SSDs are superior in handling random reads that HDDs cannot efficiently deal with. Two types of flash memory cells are available for building SSD caches, single-level cells (SLC) and multi-level cells (MLC). MLC is more appealing than SLC because it can achieve higher cache capacity at the same cost. However, we see a critical issue for SSD caches to adopt MLC NAND flash: the endurance of modern MLC NAND flash is too low to sustain datacenter workloads. In this paper, we propose DuraCache that addresses the durability issue of SSD caches. DuraCache exploits the fact that SSD caches are write-through caches in datacenters. Therefore, uncorrectable errors in SSD caches can be handled like cache misses which bring in correct data from HDD arrays. In addition, DuraCache gradually allocates more ECC parities associated with data when NAND flash reaches wearout thresholds. This allows SSD caches to continue operating by sacrificing available capacity. We conduct empirical experiments and demonstrate that DuraCache enables MLC SSD caches to achieve 4.1 years of service life assuming a TPC-C workload.

References

[1]
Datasheet: NetApp Flash Cache. NetApp. DS-2811-1211.
[2]
Flash Cache#8482;. NetApp.
[3]
ioCache#8482;. Fusion-io.
[4]
VFCache#8482;. EMC Corporation.
[5]
Western Digital settles hard-drive capacity lawsuit. FOX News, June 2006.
[6]
Considerations for choosing SLC versus MLC flash, REV A01. Technical Report 300-013-740, EMC Corporation, 2012.
[7]
Wite paper: Introduction to EMC VFCache, 2012. H10502.2.
[8]
A. Birrell, et al. A design for high-performance flash disks. SIGOPS Oper. Syst. Rev., 41(2):88--93, 2007.
[9]
Y. Cai, et al. Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. In Proc. ICCD '12.
[10]
F. Chen, et al. CAFTL: a content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives. In Proc. FAST '11.
[11]
A. Gupta, et al. Leveraging value locality in optimizing NAND flash-based SSDs. In Proc. FAST '11.
[12]
R. Koller, et al. Write policies for host-side flash caches. In Proc. FAST '13.
[13]
R.-S. Liu, et al. Optimizing NAND flash-based SSDs via retention relaxation. In Proc. FAST '12.
[14]
N. Mielke, et al. Bit error rate in NAND flash memories. In Proc. IRPS '08.
[15]
V. Mohan, et al. reFresh SSDs: Enabling high endurance, low cost flash in datacenters. Technical Report CS-2012-05, University of Virginia, 2012. Presented at FMS '12.
[16]
Y. Pan, et al. Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications. In Proc. HPCA '12.
[17]
S. Tanakamaru, et al. Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs. In Proc. IMW '10.

Cited By

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  • (2022)Self-Adapting Channel Allocation for Multiple Tenants Sharing SSD DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305637441:2(294-305)Online publication date: Feb-2022
  • (2021)Improving the Performance of Deduplication-Based Storage Cache via Content-Driven Cache Management MethodsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2020.301270432:1(214-228)Online publication date: 1-Jan-2021
  • (2021)Learning I/O Access Patterns to Improve Prefetching in SSDsMachine Learning and Knowledge Discovery in Databases: Applied Data Science Track10.1007/978-3-030-67667-4_26(427-443)Online publication date: 25-Feb-2021
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cover image ACM Conferences
DAC '13: Proceedings of the 50th Annual Design Automation Conference
May 2013
1285 pages
ISBN:9781450320719
DOI:10.1145/2463209
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 29 May 2013

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Author Tags

  1. MLC
  2. NAND flash
  3. SSD
  4. cache
  5. endurance

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2022)Self-Adapting Channel Allocation for Multiple Tenants Sharing SSD DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305637441:2(294-305)Online publication date: Feb-2022
  • (2021)Improving the Performance of Deduplication-Based Storage Cache via Content-Driven Cache Management MethodsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2020.301270432:1(214-228)Online publication date: 1-Jan-2021
  • (2021)Learning I/O Access Patterns to Improve Prefetching in SSDsMachine Learning and Knowledge Discovery in Databases: Applied Data Science Track10.1007/978-3-030-67667-4_26(427-443)Online publication date: 25-Feb-2021
  • (2020)Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory SystemsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.3015981(1-14)Online publication date: 2020
  • (2020)Low-Latency Unfolded-KES Architecture for Emerging Storage Class MemoriesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.297680667:6(2103-2113)Online publication date: Jun-2020
  • (2020)A Modeling Framework for Reliability of Erasure Codes in SSD ArraysIEEE Transactions on Computers10.1109/TC.2019.296269169:5(649-665)Online publication date: 1-May-2020
  • (2019)Who's afraid of uncorrectable bit errors? online recovery of flash errors with distributed redundancyProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358891(977-991)Online publication date: 10-Jul-2019
  • (2019)FlashieldProceedings of the 16th USENIX Conference on Networked Systems Design and Implementation10.5555/3323234.3323241(65-78)Online publication date: 26-Feb-2019
  • (2019)Revive Bad Flash-Memory Pages by HLC SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442038:5(860-873)Online publication date: May-2019
  • (2019)Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage2019 35th Symposium on Mass Storage Systems and Technologies (MSST)10.1109/MSST.2019.000-8(141-147)Online publication date: May-2019
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