research-article

HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors

Authors:

Yatish Turakhia,

Bharathwaj Raghunathan,

Siddharth Garg,

Diana MarculescuAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 173, Pages 1 - 7

https://doi.org/10.1145/2463209.2488948

Published: 29 May 2013 Publication History

Abstract

In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP with, such that the area and power budgets are met and the application performance is maximized. We consider general-purpose multi-threaded applications with a varying degree of parallelism (DOP) that can be set at run-time, and propose an accurate analytical model to predict the execution time of such applications on heterogeneous CMPs. Our experimental results illustrate that the synthesized heterogeneous dark silicon CMPs provide between 19% to 60% performance improvements over conventional homogeneous designs for variable and fixed DOP scenarios, respectively.

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Cited By

Ranjbar BSingh ASahoo SDziurzanski PKumar A(2024)Power Management of Multicore SystemsHandbook of Computer Architecture10.1007/978-981-97-9314-3_55(561-593)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_55
Ranjbar BSingh ASahoo SDziurzanski PKumar A(2023)Power Management of Multicore SystemsHandbook of Computer Architecture10.1007/978-981-15-6401-7_55-1(1-33)Online publication date: 1-Apr-2023
https://doi.org/10.1007/978-981-15-6401-7_55-1
Kulkarni AMahajan S(2022)Energy Efficient Dim and Dark Cache for Temperature Reduction of Chip MultiprocessorsRecent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering)10.2174/235209651566622042708594515:3(183-197)Online publication date: May-2022
https://doi.org/10.2174/2352096515666220427085945
Show More Cited By

Index Terms

HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
    2. Parallel architectures
2. Hardware
  1. Hardware validation

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Ranjbar BSingh ASahoo SDziurzanski PKumar A(2024)Power Management of Multicore SystemsHandbook of Computer Architecture10.1007/978-981-97-9314-3_55(561-593)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_55
Ranjbar BSingh ASahoo SDziurzanski PKumar A(2023)Power Management of Multicore SystemsHandbook of Computer Architecture10.1007/978-981-15-6401-7_55-1(1-33)Online publication date: 1-Apr-2023
https://doi.org/10.1007/978-981-15-6401-7_55-1
Kulkarni AMahajan S(2022)Energy Efficient Dim and Dark Cache for Temperature Reduction of Chip MultiprocessorsRecent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering)10.2174/235209651566622042708594515:3(183-197)Online publication date: May-2022
https://doi.org/10.2174/2352096515666220427085945
Al-Obaidy FAsad AMohammadi F(2021)A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction TechniqueInternational Journal of Parallel Programming10.1007/s10766-021-00691-5Online publication date: 24-Jan-2021
https://doi.org/10.1007/s10766-021-00691-5
Al-Obaidy FAsad AMohammadi F(2020)Improving power-performance via hybrid cache for chip many cores based on neural network prediction techniqueMicrosystem Technologies10.1007/s00542-020-05048-5Online publication date: 3-Oct-2020
https://doi.org/10.1007/s00542-020-05048-5
Asad ADorostkar AMohammadi F(2018)A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon ageEURASIP Journal on Embedded Systems10.1186/s13639-018-0086-12018:1Online publication date: 27-Jul-2018
https://doi.org/10.1186/s13639-018-0086-1
Khdr HAmrouch HHenkel J(2018)Aging-Aware BoostingIEEE Transactions on Computers10.1109/TC.2018.281601467:9(1217-1230)Online publication date: 1-Sep-2018
https://doi.org/10.1109/TC.2018.2816014
Zhang YIrving SPeng LFu XKoppelman DZhang WArdonne J(2018)Design space exploration for device and architectural heterogeneity in chip-multiprocessorsMicroprocessors & Microsystems10.1016/j.micpro.2015.07.01240:C(88-101)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2015.07.012
Kapadia NPasricha S(2017)A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon EraIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.259423825:2(534-546)Online publication date: Feb-2017
https://doi.org/10.1109/TVLSI.2016.2594238
Li MLiu WYang LChen PChen C(2017)Chip Temperature Optimization for Dark Silicon Many-Core SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.2740306(1-1)Online publication date: 2017
https://doi.org/10.1109/TCAD.2017.2740306
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