research-article

Temperature aware thread block scheduling in GPGPUs

Authors:

Tajana Simunic RosingAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 177, Pages 1 - 6

https://doi.org/10.1145/2463209.2488952

Published: 29 May 2013 Publication History

Abstract

In this paper, we present a first general purpose GPU thermal management design that consists of both hardware architecture and OS scheduler changes. Our techniques schedule thread blocks from multiple computational kernels in spatial, temporal, and spatio-temporal ways depending on the thermal state of the system. We can reduce the computation slowdown by 60% on average relative to the state of the art techniques while meeting the thermal constraints. We also extend our work to multi GPGPU cards and show improvements of 44% on average relative to existing technique.

References

[1]

J. T. Adriaens, K. Compton, N. S. Kim, and M. J. Schulte. The case for gpgpu spatial multitasking. HPCA, 2012.

Digital Library

[2]

A. Ajami, K. Banerjee, and M. Pedram. Modeling and analysis of nonuniform substrate temperature effects on global interconnects. IEEE Trans. on CAD, 2005.

Digital Library

[3]

R. Ayoub, K. Indukuri, and T. Rosing. Temperature aware dynamic workload scheduling in multisocket cpu servers. TCAD, 2011.

Digital Library

[4]

R. Ayoub, R. Nath, and T. Rosing. Jetc: Joint energy thermal and cooling management for memory and cpu subsystems in servers. HPCA, 2012.

Digital Library

[5]

D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. HPCA, 2001.

Digital Library

[6]

J. Choi, C. Cher, H. Franke, H. Hamann, A. Weger, and P. Bose. Thermal-aware task scheduling at the system software level. ISLPED, 2007.

Digital Library

[7]

A. Coskun, T. Rosing, and K. Gross. Proactive temperature management in mpsocs. ISLPED, 2008.

Digital Library

[8]

J. Donald and M. Martonosi. Techniques for multicore thermal management: Classification and new exploration. ISCA, 2006.

Digital Library

[9]

S. Heo, K. Barr, and K. Asanovic. Reducing power density through activity migration. ISLPED, 2003.

Digital Library

[10]

S. Hong and H. Kim. An integrated gpu power and performance model. ISCA, 2010.

Digital Library

[11]

M. D. Linderman, J. D. Collins, H. Wang, and T. H. Meng. Merge: a programming model for heterogeneous multi-core systems. ASPLOS, 2008.

Digital Library

[12]

NVIDIA. Gtx280 http://www.geforce.com.

[13]

J. W. Sheaffer, K. Skadron, and D. P. Luebke. Studying thermal management for graphics-processor architectures. ISPASS, 2005.

Digital Library

[14]

K. Skadron, M. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan. Temperature-aware microarchitecture: Modeling and implementation. TACO, 2004.

Digital Library

[15]

J. Wang and W. Chen. Vapor chamber in high-end vga card. IMPACT, 2010.

[16]

I. Yeo, C. Liu, and E. Kim. Predictive dynamic thermal management for multicore systems. DAC, 2008.

Digital Library

Cited By

Jiang LLiu YCheng M(2023)Fast-Accurate Full-Chip Dynamic Thermal Simulation With Fine Resolution Enabled by a Learning MethodIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322959842:8(2675-2688)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3229598
Jiang LLiu YCheng M(2021)An Effective and Accurate Data-Driven Approach for Thermal Simulation of CPUs2021 20th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm)10.1109/ITherm51669.2021.9503183(1008-1014)Online publication date: 1-Jun-2021
https://doi.org/10.1109/ITherm51669.2021.9503183
Zhang YChen SPeng LChen S(2018)NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneityIntegration, the VLSI Journal10.1016/j.vlsi.2015.04.00351:C(10-20)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2015.04.003
Show More Cited By

Index Terms

Temperature aware thread block scheduling in GPGPUs
1. Computing methodologies
  1. Computer graphics
    1. Graphics systems and interfaces
      1. Graphics processors
2. Hardware
  1. Hardware validation
  2. Integrated circuits

Recommendations

Inter-kernel Reuse-aware Thread Block Scheduling

As GPUs have become more programmable, their performance and energy benefits have made them increasingly popular. However, while GPU compute units continue to improve in performance, on-chip memories lag behind and data accesses are becoming ...
A Stall-Aware Warp Scheduling for Dynamically Optimizing Thread-level Parallelism in GPGPUs
ICS '15: Proceedings of the 29th ACM on International Conference on Supercomputing

General-Purpose Graphic Processing Units (GPGPU) have been widely used in high performance computing as application accelerators due to their massive parallelism and high throughput. A GPGPU generally contains two layers of schedulers, a cooperative-...
Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs
ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

GPUs have been proven effective for structured applications that map well to the rigid 1D-3D grid of threads in modern bulk synchronous parallel (BSP) programming languages. However, less success has been encountered in mapping data intensive irregular ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 May 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

DAC '13

Sponsor:

EDAC
SIGDA

DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
191
Total Downloads

Downloads (Last 12 months)8
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Jiang LLiu YCheng M(2023)Fast-Accurate Full-Chip Dynamic Thermal Simulation With Fine Resolution Enabled by a Learning MethodIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322959842:8(2675-2688)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3229598
Jiang LLiu YCheng M(2021)An Effective and Accurate Data-Driven Approach for Thermal Simulation of CPUs2021 20th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm)10.1109/ITherm51669.2021.9503183(1008-1014)Online publication date: 1-Jun-2021
https://doi.org/10.1109/ITherm51669.2021.9503183
Zhang YChen SPeng LChen S(2018)NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneityIntegration, the VLSI Journal10.1016/j.vlsi.2015.04.00351:C(10-20)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2015.04.003
Atoofian E(2016)Temperature-Aware Register Mapping in GPGPUs2016 IEEE Trustcom/BigDataSE/ISPA10.1109/TrustCom.2016.0252(1636-1643)Online publication date: Aug-2016
https://doi.org/10.1109/TrustCom.2016.0252
Han QFan MBai ORen SQuan G(2016)Temperature-Constrained Feasibility Analysis for Multicore SchedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.254302035:12(2082-2092)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2543020
Zhang YChen SPeng LChen S(2014)Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device HeterogeneityProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.21(577-582)Online publication date: 9-Jul-2014
https://dl.acm.org/doi/10.1109/ISVLSI.2014.21

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten