research-article

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture

Authors:

Houman Homayoun,

Nikil DuttAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 178, Pages 1 - 8

https://doi.org/10.1145/2463209.2488953

Published: 29 May 2013 Publication History

Abstract

Three dimensional (3D) integration attempts to address challenges and limitations of new technologies such as interconnect delay and power consumption. However, high power density and increased temperature in 3D architectures accelerate wearout failure mechanisms such as Negative Bias Temperature Instability (NBTI). In this paper we present VAWOM (Variation Aware WearOut Management), an approach that reduces the NBTI effect by exploiting temperature and process variation in 3D architectures. We demonstrate the efficacy of VAWOM on a two-layer 3D architecture with 4x4 cores on the first layer and 4x4 last level caches on the second layer, and show that VAWOM reduces NBTI induced threshold voltage degradation by 30% with only a small degradation in performance.

References

[1]

J. Burns et al. Design, CAD and technology challenges for future processors: 3D perspectives. In DAC, 2011.

Digital Library

[2]

A. K. Coskun et al. Dynamic thermal management in 3D multicore architectures. In DATE, 2009.

Digital Library

[3]

J. Srinivasan et al. The Impact of Technology Scaling on Lifetime Reliability. In DSN, 2004.

Digital Library

[4]

J. Abella et al. Penelope: The NBTI-Aware Processor. In MICRO, 2007.

Digital Library

[5]

A. E. Islam et al. Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation. IEEE Trans. Electron Devices, 2007.

[6]

W. Wang et al. The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst, 2010.

Digital Library

[7]

X. Zhou et al. Thermal Management for 3D Processors via Task Scheduling. In ICPP, 2008.

Digital Library

[8]

S. R. Sarangi et al. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects. IEEE Trans. Semicond. Manuf, 2008.

[9]

S. R. Nassif Modeling and analysis of manufacturing variations. In CICC, 2001.

[10]

S. V. Kumar et al. NBTI-Aware Synthesis of Digital Circuits. In DAC, 2007.

Digital Library

[11]

A. Tiwari et al. Facelift: Hiding and slowing down aging in multicores. In MICRO, 2008.

Digital Library

[12]

R. Vattikonda et al. Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design. In DAC, 2006.

Digital Library

[13]

A. Makhzan et al. Process Variation Aware Cache for Aggressive Voltage-Frequency Scaling. In DATE, 2009.

[14]

J. Srinivasan et al. Exploiting structural duplication for lifetime reliability enhancement. In ISCA, 2005.

Digital Library

[15]

J. Shin et al. A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. In ISCA, 2008.

Digital Library

[16]

L. Huang et al. Characterizing the lifetime reliability of manycore processors with core-level redundancy. In ICCAD, 2010.

Digital Library

[17]

E. Gunadi et al. Combating Aging with the Colt Duty Cycle Equalizer. In MICRO, 2010.

Digital Library

[18]

J. Sun et al. NBTI Aware Workload Balancing in Multi-core Systems. In ISQED, 2009.

Digital Library

[19]

T. Siddiqua et al. A Multi-Level Approach to Reduce the Impact of NBTI on Processor Functional Units. In GLSVLSI, 2010.

Digital Library

[20]

F. Ahmed et al. Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. In VLSI Test Symposium, 2010.

[21]

A. Ricketts et al. Investigating the impact of NBTI on different power saving cache strategies. In DATE, 2010.

Digital Library

[22]

T.-B. Chan et al. On the efficacy of NBTI mitigation techniques. In DATE, 2011.

[23]

M. A. Alam et al. A comprehensive model of PMOS NBTI degradation. Microelectronics Reliability, 2005.

[24]

Seyab et al. NBTI modeling in the framework of temperature variation. In DATE, 2010.

Digital Library

[25]

W. Huang et al. HotSpot: Thermal Modeling for CMOS VLSI Systems. IEEE Trans. Compon. Packag. Technol., 2005.

[26]

C. Zhu et al. Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. IEEE Trans. Computer Aided Design, 2008.

Digital Library

[27]

J. Wu. A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model. IEEE Transactions on Computers, 2003.

Digital Library

[28]

L. Tran et al. Heterogeneous Memory Management for 3D-DRAM and External DRAM with QoS. In ASP-DAC, 2013.

[29]

D. Reid et al. Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100,000-Sample 3-D Simulation Study. IEEE Trans. Electron Devices, 2009.

[30]

X. Fu et al. NBTI tolerant microarchitecture design in the presence of process variation. In MICRO, 2008.

Digital Library

[31]

B. Zhao et al. Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. In MICRO, 2009.

Digital Library

[32]

D. M. Tullsen. Simulation and Modeling of a Simultaneous Multithreading Processor. 1996.

[33]

M. Lis et al. Scalable, accurate multicore simulation in the 1000-core era. In ISPASS, 2011.

Digital Library

[34]

S. Li et al. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO, 2009.

Digital Library

[35]

N. Muralimanohar et al. CACTI 6.5. HP Laboratories. 2009.

[36]

H. Homayoun et al. Dynamically heterogeneous cores through 3D resource pooling. In HPCA, 2012.

Digital Library

[37]

D. Zhao et al. Temperature Aware Thread Migration in 3D Architecture with Stacked DRAM. In ISQED, 2013.

[38]

ITRS, 2009. {Online}. Available: http://www.itrs.net.

[39]

L. Zhang et al. Scheduled Voltage Scaling for Increasing Lifetime in the Presence of NBTI. In ASP-DAC, 2009.

Digital Library

[40]

H. Tajik et al. Policies for Variation Aware Wearout Management in 3D Multicore Architecture using VAWOM, CECS Technical Report 13--01, UC Irvine, 2013.

Cited By

Namazi ASafari SMohammadi SAbdollahi M(2019)SORTACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/33228994:2(1-25)Online publication date: 13-Jun-2019
https://dl.acm.org/doi/10.1145/3322899
Neshatpour KBurleson WKhajeh AHomayoun H(2018)Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal DependenceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.278080026:4(778-791)Online publication date: Apr-2018
https://doi.org/10.1109/TVLSI.2017.2780800
Namazi AAbdollahi MSafari SMohammadi SDaneshtalab M(2018)LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems2018 11th International Workshop on Network on Chip Architectures (NoCArc)10.1109/NOCARC.2018.8541223(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/NOCARC.2018.8541223
Show More Cited By

Index Terms

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

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Published: 29 May 2013

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May 29 - June 7, 2013

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Cited By

Namazi ASafari SMohammadi SAbdollahi M(2019)SORTACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/33228994:2(1-25)Online publication date: 13-Jun-2019
https://dl.acm.org/doi/10.1145/3322899
Neshatpour KBurleson WKhajeh AHomayoun H(2018)Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal DependenceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.278080026:4(778-791)Online publication date: Apr-2018
https://doi.org/10.1109/TVLSI.2017.2780800
Namazi AAbdollahi MSafari SMohammadi SDaneshtalab M(2018)LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems2018 11th International Workshop on Network on Chip Architectures (NoCArc)10.1109/NOCARC.2018.8541223(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/NOCARC.2018.8541223
Hajkazemi MTavana MMohsenin THomayoun H(2017)Heterogeneous HMC+DDRx Memory Management for Performance-Temperature TradeoffsACM Journal on Emerging Technologies in Computing Systems10.1145/310623314:1(1-21)Online publication date: 21-Sep-2017
https://dl.acm.org/doi/10.1145/3106233
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: Oct-2017
https://doi.org/10.1109/TCAD.2017.2666604
Keramati MModarressi MRezaei S(2017)Thermal management in 3d networks-on-chip using dynamic link sharingMicroprocessors & Microsystems10.1016/j.micpro.2017.05.01152:C(69-79)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1016/j.micpro.2017.05.011
Kashefi EZarandi HGordon-Ross A(2016)Postponing wearout failures in chip multiprocessors using thermal management and thread migration2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2016.7533906(1-7)Online publication date: Jun-2016
https://doi.org/10.1109/ReCoSoC.2016.7533906
Asad AOnsori SFathy MJahed-Motlagh MRaahemifar K(2016)Notice of Violation of IEEE Publication Principles - A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2016.7726817(1-6)Online publication date: May-2016
https://doi.org/10.1109/CCECE.2016.7726817
Yun JLee SYoo S(2015)Dynamic Wear Leveling for Phase-Change Memories With Endurance VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.235007323:9(1604-1615)Online publication date: Sep-2015
https://doi.org/10.1109/TVLSI.2014.2350073

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