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Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Authors:

Taigon Song,

Chang Liu,

Yarui Peng,

Sung Kyu LimAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 180, Pages 1 - 7

https://doi.org/10.1145/2463209.2488956

Published: 29 May 2013 Publication History

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Abstract

TSV-to-TSV coupling is a new parasitic element in 3D ICs and can become a significant source of signal integrity problem. Existing studies on its extraction, however, becomes highly inaccurate when handling more than two TSVs on full-chip scale. In this paper we investigate the multiple TSV-to-TSV coupling issue and propose an accurate model that can be efficiently used for full-chip extraction. Unlike the common belief that only the closest neighboring TSVs affect the victim, our study shows that non-neighboring aggressors also cause non-negligible impact. Based on this observation, we propose an effective method of reducing the overall coupling level in multiple TSV cases.

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Cited By

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Chaudhuri ABanerjee SKim JPark HKu BKannan SChakrabarty KLim S(2021)Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/346443018:1(1-37)Online publication date: 3-Nov-2021
https://dl.acm.org/doi/10.1145/3464430
Joseph JSamajdar AZhu LLeupers RLim SPionteck TKrishna T(2021)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424349(60-66)Online publication date: 7-Apr-2021
https://doi.org/10.1109/ISQED51717.2021.9424349
AMAGASAKI MIKEBE MZHAO QIIDA MSUEYOSHI T(2018)Three Dimensional FPGA Architecture with Fewer TSVsIEICE Transactions on Information and Systems10.1587/transinf.2017RCP0008E101.D:2(278-287)Online publication date: 2018
https://doi.org/10.1587/transinf.2017RCP0008
Show More Cited By

Index Terms

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs
1. Hardware
  1. Hardware validation

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DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Chaudhuri ABanerjee SKim JPark HKu BKannan SChakrabarty KLim S(2021)Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/346443018:1(1-37)Online publication date: 3-Nov-2021
https://dl.acm.org/doi/10.1145/3464430
Joseph JSamajdar AZhu LLeupers RLim SPionteck TKrishna T(2021)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424349(60-66)Online publication date: 7-Apr-2021
https://doi.org/10.1109/ISQED51717.2021.9424349
AMAGASAKI MIKEBE MZHAO QIIDA MSUEYOSHI T(2018)Three Dimensional FPGA Architecture with Fewer TSVsIEICE Transactions on Information and Systems10.1587/transinf.2017RCP0008E101.D:2(278-287)Online publication date: 2018
https://doi.org/10.1587/transinf.2017RCP0008
Lee YPan KChen C(2017)NaPerIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.264523025:5(1703-1713)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2645230
Jang JCheong MAhn JLim SKang S(2017)Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay EstimationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.262381025:3(1178-1182)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2623810
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: Oct-2017
https://doi.org/10.1109/TCAD.2017.2666604
Song TLiu CPeng YLim S(2016)Full-Chip Signal Integrity Analysis and Optimization of 3-D ICsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.247109824:5(1636-1648)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2471098
Jun Li Xing-Chang Wei Er-Ping Li (2016)Accurate Field-Circuit Hybrid Modeling of High-Density Through Glass Via Arrays by Using Perfect Magnetic Conductors and Cylindrical Mode ExpansionIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2015.25033626:1(100-108)Online publication date: Jan-2016
https://doi.org/10.1109/TCPMT.2015.2503362
Yaghini PEghbal AYazdi SBagherzadeh NGreen M(2016)Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICsIEEE Transactions on Computers10.1109/TC.2015.249855065:3(693-705)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TC.2015.2498550
Ramadan TYahya EDessouky MIsmail Y(2016)Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7538951(1930-1933)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7538951
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Recommendations

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling

Efficient characterization of TSV-to-transistor noise coupling in 3D ICs

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