research-article

An accurate semi-analytical framework for full-chip TSV-induced stress modeling

Authors:

David Z. PanAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 181, Pages 1 - 8

https://doi.org/10.1145/2463209.2488957

Published: 29 May 2013 Publication History

Abstract

TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis for the stress of simple TSV placement, but is not scalable to larger designs due to its expensive memory consumption and high run time. On the contrary, linear superposition method is efficient to analyze stress in full-chip scale, but sometimes it fails to provide an accurate estimation since it neglects the stress induced by interactions between TSVs. In this paper we propose an accurate two-stage semi-analytical framework for full-chip TSV-induced stress modeling. In addition to the linear superposition, we characterize the stress induced by interactions between TSVs to provide more accurate full-chip modeling. Experimental results demonstrate that the proposed framework can significantly improve the accuracy of linear superposition method with reasonable overhead in run time.

References

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K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim, "Stress-driven 3D-IC placement with TSV keep-out zone and regularity study," in Proc. ICCAD, 2010.

Digital Library

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J. Mitra, M. Jung, S.-K. Ryu, R. Huang, S. K. Lim, and D. Z. Pan, "A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs," in Proc. ECTC, 2011.

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Cited By

Zhou HZhu HCui TPan DZhou DZeng X(2018)Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element MethodIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.281141726:7(1312-1325)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1109/TVLSI.2018.2811417

Index Terms

An accurate semi-analytical framework for full-chip TSV-induced stress modeling
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 29 May 2013

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DAC '13: The 50th Annual Design Automation Conference 2013

May 29 - June 7, 2013

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Cited By

Zhou HZhu HCui TPan DZhou DZeng X(2018)Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element MethodIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.281141726:7(1312-1325)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1109/TVLSI.2018.2811417

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