ABSTRACT
As hardware parallelism continues to increase, CPU caches can no longer be considered as a transparent, hardware-level performance optimization. Cache impact on performance, in particular in the face of false sharing, is completely dependent on the software that is executing. To effectively support parallel workloads on cache coherent hardware, the operating system must begin to treat the CPU cache like other shared hardware resources, and manage it appropriately.
We demonstrate a prototype example of such support by describing Plastic, a software-based system that detects, diagnoses, and transparently repairs false sharing as it occurs in running applications. Plastic solves two challenging problems. First, it is capable of rapid, low-overhead detection and diagnosis of false sharing in unmodified, running applications. Second, it resolves identified instances of false sharing by providing a sub-page granularity memory remapping facility within the system. Our implementation is capable of identifying and repairing pathological false sharing in under one second of execution and achieves speedups of 3-6x on known examples of false sharing in parallel benchmarks.
- P. Barham, B. Dragovic, K. Fraser, S. Hand, T. L. Harris, A. Ho, R. Neugebauer, I. Pratt, and A. Warfield. Xen and the art of virtualization. In SOSP, 2003. Google ScholarDigital Library
- A. Baumann, P. Barham, P.-E. Dagand, T. Harris, R. Isaacs, S. Peter, T. Roscoe, A. Schupbach, and A. Singhania. The multikernel: a new OS architecture for scalable multicore systems. In SOSP, 2009. Google ScholarDigital Library
- T. Bergan, N. Hunt, L. Ceze, and S. Gribble. Deterministic process groups in dos. In OSDI, 2010. Google ScholarDigital Library
- A. R. Bernat and B. P. Miller. Anywhere, any-time binary instrumentation. In PASTE, 2011. Google ScholarDigital Library
- C. Bienia and K. Li. Parsec 2.0: A new benchmark suite for chip-multiprocessors. In Workshop on Modeling, Benchmarking and Simulation, 2009.Google Scholar
- W. J. Bolosky and M. L. Scott. False sharing and its effect on shared memory performance. In SEDMS, 1993. Google ScholarDigital Library
- S. Boyd-Wickizer, A. T. Clements, Y. Mao, A. Pesterev, M. F. Kaashoek, R. Morris, and N. Zeldovich. An analysis of linux scalability to many cores. In OSDI, 2010. Google ScholarDigital Library
- D. Bruening, T. Garnett, and S. Amarasinghe. An infrastructure for adaptive dynamic optimization. In CGO, 2003. Google ScholarDigital Library
- M. Burrows, U. Erlingsson, S.-T. A. Leung, M. T. Vandevoorde, C. A. Waldspurger, K. Walker, and W. E. Weihl. Efficient and flexible value sampling. In ASPLOS, 2000. Google ScholarDigital Library
- B. Dawes, D. Abrahams, and R. Rivera. Boost C++ libraries. http://www.boost.org, 2009.Google Scholar
- D. Dice. False sharing induced by card table marking, February 2011. URL https://blogs.oracle.com/dave/entry/false_sharing_induced_by_card.Google Scholar
- U. Erlingsson, M. Abadi, M. Vrable, M. Budiu, and G. C. Necula. XFI: software guards for system address spaces. In OSDI, 2006. Google ScholarDigital Library
- B. Ford and R. Cox. Vx32: lightweight user-level sandboxing on the x86. In USENIX ATC, 2008. Google ScholarDigital Library
- J. L. Greathouse, Z. Ma, M. I. Frank, R. Peri, and T. Austin. Demand-driven software race detection using hardware performance counters. In ISCA, 2011. Google ScholarDigital Library
- J. L. Greathouse, H. Xin, Y. Luo, and T. Austin. A case for unlimited watchpoints. In ASPLOS, 2012. Google ScholarDigital Library
- S. M. Gunther and J. Weidendorfer. Assessing cache false sharing effects by dynamic binary instrumentation. In WBIA, 2009. Google ScholarDigital Library
- J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. 5 edition, 2011. Google ScholarDigital Library
- M. Herlihy and J. Moss. System for achieving atomic non-sequential multi-word operations in shared memory, June 27 1995. US Patent 5,428,761.Google Scholar
- J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, and et al. A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. IEEE, 2010.Google Scholar
- Intel. Avoiding and identifying false sharing among threads, November 2011. URL http://software.intel.com/en-us/articles/avoiding-and-identifying-false-sharing-among-threads/.Google Scholar
- Intel. Intel performance tuning utility, October 2012. URL http://software.intel.com/en-us/articles/intel-performance-tuning-utility/.Google Scholar
- A. Jaleel, R. S. Cohn, C. keung Luk, and B. Jacob. CMPSim: A pin-based on-the-fly multi-core cache simulator. In MOBS, 2008.Google Scholar
- D. Levinthal. Performance analysis guide for Intel Core i7 processor and Intel Xeon 5500 processors, 2008.Google Scholar
- T. Liu and E. D. Berger. Sheriff: precise detection and automatic mitigation of false sharing. In OOPSLA, 2011. Google ScholarDigital Library
- C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In PLDI, 2005. Google ScholarDigital Library
- M. Martin, M. Hill, and D. Sorin. Why on-chip cache coherence is here to stay. CACM, 55(7):78--89, 2012. Google ScholarDigital Library
- mcmcc. false sharing in boost::detail::spinlock_pool?, June 2012. URL http://stackoverflow.com/questions/11037655/false-sharing-in-boostdetailspinlock-pool.Google Scholar
- D. Molka, D. Hackenberg, R. Schone, and M. S. Muller. Memory performance and cache coherency effects on an Intel Nehalem multiprocessor system. In PACT, 2009. Google ScholarDigital Library
- K. Moore, J. Bobba, M. Moravan, M. Hill, and D. Wood. Logtm: Log-based transactional memory. In HPCA, 2006.Google ScholarCross Ref
- R. J. Moore. A universal dynamic trace for linux and other operating systems. In USENIX ATC, 2001. Google ScholarDigital Library
- M. Olszewski, K. Mierle, A. Czajkowski, and A. D. Brown. JIT instrumentation: a novel approach to dynamically instrument operating systems. In EuroSys, 2007. Google ScholarDigital Library
- M. Olszewski, Q. Zhao, D. Koh, J. Ansel, and S. P. Amarasinghe. Aikido: Accelerating shared data dynamic analyses. In ASPLOS, 2012. Google ScholarDigital Library
- M. S. Papamarcos and J. H. Patel. A low-overhead coherence solution for multiprocessors with private cache memories. In ISCA, 1984. Google ScholarDigital Library
- A. Pesterev, N. Zeldovich, and R. T. Morris. Locating cache performance bottlenecks using data profiling. In EuroSys, 2010. Google ScholarDigital Library
- C. Ranger, R. Raghuraman, A. Penmetsa, G. Bradski, and C. Kozyrakis. Evaluating MapReduce for multi-core and multiprocessor systems. In HPCA, 2007. Google ScholarDigital Library
- A. Tamches and B. P. Miller. Fine-grained dynamic instrumentation of commodity operating system kernels. In OSDI, 1999. Google ScholarDigital Library
- J. Tao and W. Karl. CacheIn: A toolset for comprehensive cache inspection. In International Conference on Computational Science, 2005. Google ScholarDigital Library
- C. Thacker. Beehive: A many-core computer for FPGAs (v5). MSR Silicon Valley, Jan 2010. URL http://projects.csail.mit.edu/beehive/BeehiveV5.pdf.Google Scholar
- B. Yee, D. Sehr, G. Dardyk, J. Chen, R. Muth, T. Ormandy, S. Okasaka, N. Narula, and N. Fullagar. Native client: A sandbox for portable, untrusted x86 native code. In IEEE S&P, 2009. Google ScholarDigital Library
- Q. Zhao, D. Koh, S. Raza, D. Bruening, W.-F. Wong, and S. Amarasinghe. Dynamic cache contention detection in multi-threaded applications. In VEE, 2011. Google ScholarDigital Library
Index Terms
- Whose cache line is it anyway?: operating system support for live detection and repair of false sharing
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