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Software-defined massive multicore networking via freespace optical interconnect

Published: 14 May 2013 Publication History

Abstract

This paper presents a new frontier where future computer systems can continue to evolve as CMOS technology reaches its fundamental performance and density scaling limits. Our idea adopts freespace circuit-switched optical interconnect in massive multicore networking on chips and modules to flexibly configure private cache-coherent networks for allocated groups of cores in a software-defined manner. The proposed scheme can avoid networking inefficiencies due to the core resource fragmentation by providing deterministically lower latencies and higher bandwidth while advancing the technology roadmap with lower power consumption and improved cooling. We also discuss implementation plan and challenges for our proposal.

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  • (2014)Multicore processors: Status quo and future directions2014 10th International Computer Engineering Conference (ICENCO)10.1109/ICENCO.2014.7050422(1-4)Online publication date: Dec-2014
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      cover image ACM Conferences
      CF '13: Proceedings of the ACM International Conference on Computing Frontiers
      May 2013
      302 pages
      ISBN:9781450320535
      DOI:10.1145/2482767
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 14 May 2013

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      Author Tags

      1. freespace interconnect
      2. multicore networking
      3. technology scaling

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      CF'13: Computing Frontiers Conference
      May 14 - 16, 2013
      Ischia, Italy

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      CF '13 Paper Acceptance Rate 26 of 49 submissions, 53%;
      Overall Acceptance Rate 273 of 785 submissions, 35%

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      View all
      • (2017)Toward Human-Scale Brain Computing Using 3D Wafer Scale IntegrationACM Journal on Emerging Technologies in Computing Systems10.1145/297674213:3(1-21)Online publication date: 20-Apr-2017
      • (2014)Core Technologies for Breaking into Cognitive Computing EraJournal of The Japan Institute of Electronics Packaging10.5104/jiep.17.15617:3(156-162)Online publication date: 2014
      • (2014)Multicore processors: Status quo and future directions2014 10th International Computer Engineering Conference (ICENCO)10.1109/ICENCO.2014.7050422(1-4)Online publication date: Dec-2014
      • (2014)An Energy-Efficient Computing Approach by Filling the Connectome GapUnconventional Computation and Natural Computation10.1007/978-3-319-08123-6_19(229-241)Online publication date: 2014

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