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Coordinating prefetching and STT-RAM based last-level cache management for multicore systems

Published: 02 May 2013 Publication History

Abstract

Data prefetching is a common mechanism to mitigate the bottleneck of off-chip memory bandwidth in modern computing systems. Unfortunately, the side effects of prefetching are an additional burden on off-chip communication and increased cache write operations. With the proposal of spin-transfer torque random access memory (STT-RAM) based last-level caches (LLCs) for their high density and low power consumption, the increase of write pressure to the cache from prefetching coupled with the characteristically long write access compared with traditional SRAM caches exacerbates the performance cost of prefetching schemes. In this work, we propose two orthogonal techniques to reduce the negative performance impact induced by aggressive prefetching on multicore systems employing STT-RAM based LLC. First, basic priority assignment prioritizes the different types of access requests of LLC by their criticality and responds to them based on priority. Second, priority boosting differentiates requests by application and prioritizes the relatively few requests from applications with non-intensive accesses to the LLC, which usually creates the most severe performance degradation in multi-core systems. Combining these two prioritization policies can alleviate the negative effect induced by aggressive prefetching. Our results show that these techniques can achieve an 8.3 average application speedup compared to a baseline, prefetch only design without prioritization.

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Cited By

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  • (2023)Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systemsDesign Automation for Embedded Systems10.1007/s10617-023-09272-w27:4(303-331)Online publication date: 5-May-2023
  • (2020)Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management PolicyIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.294724267:1(108-120)Online publication date: Jan-2020
  • (2020)Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301288039:11(4115-4128)Online publication date: Nov-2020
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    cover image ACM Conferences
    GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
    May 2013
    368 pages
    ISBN:9781450320320
    DOI:10.1145/2483028
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 02 May 2013

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    Author Tags

    1. cache management
    2. prefetching
    3. stt-ram

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2023)Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systemsDesign Automation for Embedded Systems10.1007/s10617-023-09272-w27:4(303-331)Online publication date: 5-May-2023
    • (2020)Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management PolicyIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.294724267:1(108-120)Online publication date: Jan-2020
    • (2020)Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301288039:11(4115-4128)Online publication date: Nov-2020
    • (2020)A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289770739:4(803-815)Online publication date: Apr-2020
    • (2017)ThermosiphonProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199763(474-481)Online publication date: 13-Nov-2017
    • (2017)FlowPaP and FlowReRACM Transactions on Embedded Computing Systems10.1145/312653216:5s(1-20)Online publication date: 27-Sep-2017
    • (2017)Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203815(474-481)Online publication date: Nov-2017
    • (2017)Obfuscated red-black tree: Decoupling search trees to make them friendly for nonvolatile memories in one-memory systems2017 International Conference on Applied System Innovation (ICASI)10.1109/ICASI.2017.7988178(1075-1078)Online publication date: May-2017
    • (2016)Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage LifetimeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254006924:10(3118-3131)Online publication date: 1-Oct-2016
    • (2016)Architecture design with STT-RAM: Opportunities and challenges2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7427997(109-114)Online publication date: Jan-2016
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