skip to main content
10.1145/2485922.2485961acmotherconferencesArticle/Chapter ViewAbstractPublication PagesiscaConference Proceedingsconference-collections
research-article

Zombie memory: Extending memory lifetime by reviving dead blocks

Published: 23 June 2013 Publication History

Abstract

Zombie is an endurance management framework that enables a variety of error correction mechanisms to extend the lifetimes of memories that suffer from bit failures caused by wearout, such as phase-change memory (PCM). Zombie supports both single-level cell (SLC) and multi-level cell (MLC) variants. It extends the lifetime of blocks in working memory pages (primary blocks) by pairing them with spare blocks, i.e., working blocks in pages that have been disabled due to exhaustion of a single block's error correction resources, which would be 'dead' otherwise. Spare blocks adaptively provide error correction resources to primary blocks as failures accumulate over time. This reduces the waste caused by early block failures, making working blocks in discarded pages a useful resource. Even though we use PCM as the target technology, Zombie applies to any memory technology that suffers stuck-at cell failures.
This paper describes the Zombie framework, a combination of two new error correction mechanisms (ZombieXOR for SLC and ZombieMLC for MLC) and the extension of two previously proposed SLC mechanisms (ZombieECP and ZombieERC). The result is a 58% to 92% improvement in endurance for Zombie SLC memory and an even more impressive 11x to 17x improvement for ZombieMLC, both with performance overheads of only 0.1% when memories using prior error correction mechanisms reach end of life.

References

[1]
S. Ahn et al., "Highly manufacturable high density phase change memory of 64mb and beyond," in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, Dec. 2004, pp. 907--910.
[2]
N. Alon and S. Lovett, "Almost k-wise vs. k-wise independent permutations and uniformity for general group actions," in International Workshop on Randomization and Computation (RANDOM), 2012.
[3]
G. Atwood, "The evolution of phase change memory," Micron, Tech. Rep., 2010.
[4]
A. Barg and A. Mazumdar, "Codes in permutations and error correction for rank modulation," IEEE Transactions on Information Theory, vol. 56, no. 7, pp. 3158--3165, July 2010.
[5]
G. W. Burr et al., "Phase change memory technology," Journal of Vacuum Science and Technology B, vol. 28, no. 2, pp. 223--262, 2010.
[6]
S. Cho and H. Lee, "Flip-n-write: a simple deterministic technique to improve pram write performance, energy and endurance," in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2009.
[7]
R. Datta and N. A. Touba, "Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories," in VLSI Test Symposium, 2011.
[8]
J. D. Davis et al., "Supplement to Zombie Memory: Extending memory lifetime by reviving dead blocks," Technical Report: MSR-TR-2013-47, Microsoft Research Silicon Valley, 2013.
[9]
A. Gabizon and R. Shaltiel, "Invertible zero-error dispersers and defective memory with stuck-at errors," in International Workshop on Randomization and Computation (RANDOM), 2012.
[10]
J. L. Henning, "SPEC CPU2006 benchmark descriptions," ACM Computer Architecture News, vol. 34, no. 4, Sep. 2006, http://www.spec.org/cpu2006/publications/CPU2006benchmarks.pdf.
[11]
E. Horowitz, "Modular arithmetic and finite field theory: A tutorial," in Proceedings of the second ACM Symposium on Symbolic and Algebraic Manipulation, ser. SYMSAC '71. New York, NY, USA: ACM, 1971, pp. 188--194. {Online}. Available: http://doi.acm.org/10.1145/800204.806287
[12]
Y. Hwang et al., "Full integration and reliability evaluation of phase-change RAM based on 0.24um-cmos technologies," in 2003 Symposium on VLSI Technology, Jun. 2003.
[13]
D. Ielmini et al., "Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, dec. 2007, pp. 939--942.
[14]
D. Ielmini et al., "Recovery and drift dynamics of resistance and threshold voltages in phase-change memories," Electron Devices, IEEE Transactions on, vol. 54, no. 2, pp. 308--315, feb. 2007.
[15]
E. Ipek et al., "Dynamically replicated memory: building reliable systems from nanoscale resistive memories," in Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, Mar. 2010.
[16]
ITRS, "Emerging research devices," International Technology Roadmap for Semiconductors, Tech. Rep., 2009.
[17]
A. N. Jacobvitz et al., "Coset coding to improve the lifetime of memory," in IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013.
[18]
A. Jiang et al., "Rank modulation for flash memories," Information Theory, IEEE Transactions on, vol. 55, no. 6, 2009.
[19]
A. V. Kuznetsov and B. S. Tsybakov, "Coding in a memory with defective cells," Problems of Information Transmission, vol. 10, no. 2, pp. 132--138, 1974.
[20]
B. C. Lee et al., "Architecting phase change memory as a scalable dram alternative," in Proceedings of the 36th Annual International Symposium on Computer Architecture, Jun. 2009.
[21]
C.-K. Luk et al., "Pin: building customized program analysis tools with dynamic instrumentation," in Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, Jun. 2005.
[22]
F. J. MacWilliams and N. J. A. Sloane, The Theory of Error Correcting Codes. Amsterdam, New York: North Holland, 1977.
[23]
N. Papandreou et al., "Drift-tolerant multilevel phase-change memory," in Proceedings of the 3rd IEEE International Memory Workshop, May 2011, pp. 1--4.
[24]
M. K. Qureshi, "Pay-as-You-Go: Low overhead hard-error correction for phase change memories," in Proceedings of the 44th International Symposium on Microarchitecture, 2011.
[25]
M. K. Qureshi et al., "Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling," in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2009.
[26]
M. K. Qureshi et al., "Scalable high performance main memory system using phase-change memory technology," in Proceedings of the 36th Annual International Symposium on Computer Architecture, Jun. 2009.
[27]
M. K. Qureshi et al., "Morphable memory system: a robust architecture for exploiting multi-level phase change memories," in Proceedings of the 37th Annual International Symposium on Computer Architecture, Jun. 2010.
[28]
D. Ralph and M. Stiles, "Spin transfer torques," Journal of Magnetism and Magnetic Materials, vol. 320, no. 7, pp. 1190--1216, 2008. {Online}. Available: http://www.sciencedirect.com/science/article/pii/S0304885307010116.
[29]
S. Raoux et al., "Phase-change random access memory: a scalable technology," IBM Journal of Research and Development, vol. 52, pp. 465--479, Jul. 2008.
[30]
S. Schechter et al., "Use ecp, not ecc, for hard failures in resistive memories," in Proceedings of the 37th Annual International Symposium on Computer Architecture, Jun. 2010.
[31]
N. H. Seong et al., "SAFER: Stuck-at-fault error recovery for memories," in Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2010.
[32]
N. H. Seong et al., "Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping," in Proceedings of the 37th Annual International Symposium on Computer Architecture, Jun. 2010.
[33]
D. B. Strukov et al., "The missing memristor found," Nature, vol. 453, pp. 80--83, 2008.
[34]
B. S. Tsybakov, "Additive group codes for defect correction," Problems of Information Transmission, vol. 11, no. 1, pp. 88--90, 1975.
[35]
B.-D. Yang et al., "A low power phase-change random access memory using a data-comparison write scheme," in IEEE International Symposium on Circuits and Systems, May 2007.
[36]
Y. Yehezkeally and M. Schwartz, "Snake-in-the-box codes for rank modulation," Information Theory, IEEE Transactions on, vol. 58, no. 8, Aug 2012.
[37]
D. H. Yoon et al., "FREE-p: Protecting non-volatile memory against both hard and soft failures," in Proceedings of the 17th Symposium on High Performance Computer Architecture, 2011.
[38]
W. Zhang and T. Li, "Characterizing and mitigating the impact of process variations on phase change based memory systems," in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2009.
[39]
W. Zhang and T. Li, "Exploring phase change memory and 3d die-stacking for power/thermal friendly, fast and durable memory architectures," in Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, Sep. 2009.
[40]
P. Zhou et al., "A durable and energy efficient main memory using phase change memory technology," in Proceedings of the 36th Annual International Symposium on Computer Architecture, Jun. 2009.

Cited By

View all
  • (2025)SMART-WRITE: Adaptive Learning-Based Write Energy Optimization for Phase Change Memory2025 IEEE 15th Annual Computing and Communication Workshop and Conference (CCWC)10.1109/CCWC62904.2025.10903957(00640-00648)Online publication date: 6-Jan-2025
  • (2024)WIRE: Write Energy Reduction via Encoding in Phase Change Main Memories (PCM)Proceedings of the Future Technologies Conference (FTC) 2024, Volume 310.1007/978-3-031-73125-9_38(599-615)Online publication date: 8-Nov-2024
  • (2023)SW-PCM: Graceful Degradation Support in PCM Main Memories by Using Swaption MechanismProceedings of the Future Technologies Conference (FTC) 2023, Volume 310.1007/978-3-031-47457-6_34(514-531)Online publication date: 9-Nov-2023
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture
June 2013
686 pages
ISBN:9781450320795
DOI:10.1145/2485922
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 41, Issue 3
    ICSA '13
    June 2013
    666 pages
    ISSN:0163-5964
    DOI:10.1145/2508148
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

  • IEEE CS

In-Cooperation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 2013

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. drift tolerance
  2. error correction
  3. phase-change memory

Qualifiers

  • Research-article

Funding Sources

Conference

ISCA'13
Sponsor:

Acceptance Rates

ISCA '13 Paper Acceptance Rate 56 of 288 submissions, 19%;
Overall Acceptance Rate 543 of 3,203 submissions, 17%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)55
  • Downloads (Last 6 weeks)8
Reflects downloads up to 08 Mar 2025

Other Metrics

Citations

Cited By

View all
  • (2025)SMART-WRITE: Adaptive Learning-Based Write Energy Optimization for Phase Change Memory2025 IEEE 15th Annual Computing and Communication Workshop and Conference (CCWC)10.1109/CCWC62904.2025.10903957(00640-00648)Online publication date: 6-Jan-2025
  • (2024)WIRE: Write Energy Reduction via Encoding in Phase Change Main Memories (PCM)Proceedings of the Future Technologies Conference (FTC) 2024, Volume 310.1007/978-3-031-73125-9_38(599-615)Online publication date: 8-Nov-2024
  • (2023)SW-PCM: Graceful Degradation Support in PCM Main Memories by Using Swaption MechanismProceedings of the Future Technologies Conference (FTC) 2023, Volume 310.1007/978-3-031-47457-6_34(514-531)Online publication date: 9-Nov-2023
  • (2021)Write Prediction for Persistent Memory SystemsProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00025(242-257)Online publication date: 26-Sep-2021
  • (2021)A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future DirectionsJournal of Computer Science and Technology10.1007/s11390-020-0780-z36:1(4-32)Online publication date: 30-Jan-2021
  • (2020)CentaurProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/33921464:2(1-25)Online publication date: 12-Jun-2020
  • (2020)WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders2020 IEEE 38th International Conference on Computer Design (ICCD)10.1109/ICCD50377.2020.00044(187-196)Online publication date: Oct-2020
  • (2020)SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile MemoryIEEE Access10.1109/ACCESS.2020.29888898(76130-76142)Online publication date: 2020
  • (2019)Binary StarProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358262(807-820)Online publication date: 12-Oct-2019
  • (2019)A Survey on PCM Lifetime Enhancement SchemesACM Computing Surveys10.1145/333225752:4(1-38)Online publication date: 30-Aug-2019
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media