research-article

Reduced hardware transactions: a new approach to hybrid transactional memory

Authors:

Alexander Matveev,

Nir ShavitAuthors Info & Claims

SPAA '13: Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures

Pages 11 - 22

https://doi.org/10.1145/2486159.2486188

Published: 23 July 2013 Publication History

Abstract

For many years, the accepted wisdom has been that the key to adoption of best-effort hardware transactions is to guarantee progress by combining them with an all software slow-path, to be taken if the hardware transactions fail repeatedly. However, all known generally applicable hybrid transactional memory solutions suffer from a major drawback: the coordination with the software slow-path introduces an unacceptably high instrumentation overhead into the hardware transactions.

This paper overcomes the problem using a new approach which we call reduced hardware (RH) transactions. Instead of an all-software slow path, in RH transactions part of the slow-path is executed using a smaller hardware transaction. The purpose of this hardware component is not to speed up the slow-path (though this is a side effect). Rather, using it we are able to eliminate almost all of the instrumentation from the common hardware fast-path, making it virtually as fast as a pure hardware transaction. Moreover, the "mostly software" slow-path is obstruction-free (no locks), allows execution of long transactions and protected instructions that may typically cause hardware transactions to fail, allows complete concurrency between hardware and software transactions, and uses the shorter hardware transactions only to commit.

Finally, we show how to easily default to a mode allowing an all-software slow-slow mode in case the "mostly software" slow-path fails to commit.

References

[1]

D. Dice A. Matveev and N. Shavit. Implicit privatization using private transactions. In Transact 2010, Paris, France, 2010.

[2]

Hagit Attiya and Eshcar Hillel. A single-version stm that is multi-versioned permissive. Theory Comput. Syst., 51(4):425--446, 2012.

[3]

Hillel Avni and Nir Shavit. Maintaining consistent transactional states without a global clock. In SIROCCO, pages 131--140, 2008.

Digital Library

[4]

Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, and Etienne Riviàre. Evaluation of amd's advanced synchronization facility within a complete transactional memory stack. In Proceedings of the 5th European conference on Computer systems, pages 27--40, New York, NY, USA, 2010. ACM.

Digital Library

[5]

Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, and Michael F. Spear. Hybrid norec: a case study in the effectiveness of best effort hardware transactional memory. SIGPLAN Not., 46(3):39--52, March 2011.

[6]

Luke Dalessandro, Michael F. Spear, and Michael L. Scott. Norec: streamlining stm by abolishing ownership records. In Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP '10, pages 67--78, New York, NY, USA, 2010. ACM.

Digital Library

[7]

Peter Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, and Daniel Nussbaum. Hybrid transactional memory. SIGPLAN Not., 41(11):336--346, October 2006.

Digital Library

[8]

D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In Proc. of the 20th International Symposium on Distributed Computing (DISC 2006), pages 194--208, 2006.

Digital Library

[9]

D. Dice and N. Shavit. Tlrw: Return of the read-write lock. In Transact 2009, Raleigh, North Carolina, USA, 2009.

[10]

Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, and Anthony Nguyen. Hybrid transactional memory. In Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, PPoPP '06, pages 209--220, New York, NY, USA, 2006. ACM.

Digital Library

[11]

Yossi Lev, Mark Moir, and Dan Nussbaum. Phtm: Phased transactional memory. In Workshop on Transactional Computing (Transact), 2007. research.sun.com/scalable/pubs/TRANSACT2007PhTM.pdf, 2007.

[12]

C. Fetzer P. Felber and T. Riegel. Dynamic performance tuning of word-based software transactional memory. In PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, pages 237--246, New York, NY, USA, 2008. ACM.

Digital Library

[13]

Torvald Riegel, Patrick Marlier, Martin Nowack,Pascal Felber, and Christof Fetzer. Optimizing hybrid transactional memory: the importance of nonspeculative operations. In Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures, SPAA '11, pages 53--64, New York, NY, USA, 2011. ACM.

Digital Library

[14]

Arrvindh Shriraman, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott, David Eisenstat, Christopher Heriot, William N. Scherer III, and Michael F. Spear. Hardware acceleration of software transactional memory. Technical report, DEPT. OF COMPUTER SCIENCE, UNIV. OF ROCHESTER, 2006.

[15]

P. Felber T. Riegel and C. Fetzer. A lazy snapshot algorithm with eager validation. In 20th International Symposium on Distributed Computing (DISC), September 2006.

Digital Library

[16]

Amy Wang, Matthew Gaudet, Peng Wu, José Nelson Amaral, Martin Ohmacht, Christopher Barton, Raul Silvera, and Maged Michael. Evaluation of blue gene/q hardware support for transactional memories. In Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12, pages 127--136, New York, NY, USA, 2012. ACM.

Digital Library

[17]

Web. Intel tsx http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell, 2012.

Cited By

Li YLiu HGao JZhang JGuan ZChen Z(2024)Accelerating block lifecycle on blockchain via hardware transactional memoryJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104779184(104779)Online publication date: Feb-2024
https://doi.org/10.1016/j.jpdc.2023.104779
Morales CHonorio BBaldassin AAraujo G(2021)Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD53543.2021.00016(44-53)Online publication date: Oct-2021
https://doi.org/10.1109/SBAC-PAD53543.2021.00016
Yates RScott MHollingsworth JKeidar I(2019)Leveraging hardware TM in HaskellProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295711(94-106)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.1145/3293883.3295711
Show More Cited By

Index Terms

Reduced hardware transactions: a new approach to hybrid transactional memory
1. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Concurrency control
        Multiprocessing / multiprogramming / multitasking
        Multithreading
        Process synchronization

Recommendations

Invyswell: a hybrid transactional memory for haswell's restricted transactional memory
PACT '14: Proceedings of the 23rd international conference on Parallel architectures and compilation

The Intel Haswell processor includes restricted transactional memory (RTM), which is the first commodity-based hardware transactional memory (HTM) to become publicly available. However, like other real HTMs, such as IBM's Blue Gene/Q, Haswell's RTM is ...
Grasping the gap between blocking and non-blocking transactional memories

Transactional memory (TM) is an inherently optimistic abstraction: it allows concurrent processes to execute sequences of shared-data accesses (transactions) speculatively, with an option of aborting them in the future. Early TM designs avoided using ...
Looking for efficient implementations of concurrent objects
PaCT'11: Proceedings of the 11th international conference on Parallel computing technologies

As introduced by Taubenfeld, a contention-sensitive implementation of a concurrent object is an implementation such that the overhead introduced by locking is eliminated in the common cases, i.e., when there is no contention or when the operations ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

SPAA '13: Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures

July 2013

348 pages

ISBN:9781450315722

DOI:10.1145/2486159

General Chair:
Guy Blelloch
Carnegie Mellon University, USA
,
Program Chair:
Berthold Vöcking
RWTH Aachen University, Germany

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 July 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

SPAA '13

Sponsor:

SPAA '13: 25th ACM Symposium on Parallelism in Algorithms and Architectures

July 23 - 25, 2013

Québec, Montréal, Canada

Acceptance Rates

SPAA '13 Paper Acceptance Rate 31 of 130 submissions, 24%;

Overall Acceptance Rate 447 of 1,461 submissions, 31%

Upcoming Conference

SPAA '25

Sponsor:
sigact
sigact

37th ACM Symposium on Parallelism in Algorithms and Architectures

July 28 - August 1, 2025

Portland , OR , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
277
Total Downloads

Downloads (Last 12 months)12
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Li YLiu HGao JZhang JGuan ZChen Z(2024)Accelerating block lifecycle on blockchain via hardware transactional memoryJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104779184(104779)Online publication date: Feb-2024
https://doi.org/10.1016/j.jpdc.2023.104779
Morales CHonorio BBaldassin AAraujo G(2021)Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD53543.2021.00016(44-53)Online publication date: Oct-2021
https://doi.org/10.1109/SBAC-PAD53543.2021.00016
Yates RScott MHollingsworth JKeidar I(2019)Leveraging hardware TM in HaskellProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295711(94-106)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.1145/3293883.3295711
de Carvalho JAraujo GBaldassin A(2019)The Case for Phase-Based Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286171230:2(459-472)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1109/TPDS.2018.2861712
Park JBaek W(2019)Analyzing and optimizing the performance and energy efficiency of transactional scientific applications on large-scale NUMA systems with HTM supportJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.12.007127:C(1-17)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1016/j.jpdc.2018.12.007
Park JBaek W(2018)Quantifying the Performance and Energy-Efficiency Impact of Hardware Transactional Memory on Scientific Applications on Large-Scale NUMA Systems2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2018.00090(804-813)Online publication date: May-2018
https://doi.org/10.1109/IPDPS.2018.00090
Raminhas PIssa SRomano PEl-Araby EEl-Ghazawi TPanda D(2018)Enhancing efficiency of hybrid transactional memory via dynamic data partitioning schemesProceedings of the 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing10.1109/CCGRID.2018.00020(51-61)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1109/CCGRID.2018.00020
Alistarh DKopinsky JKuznetsov PRavi SShavit N(2018)Inherent limitations of hybrid transactional memoryDistributed Computing10.1007/s00446-017-0305-331:3(167-185)Online publication date: 1-Jun-2018
https://dl.acm.org/doi/10.1007/s00446-017-0305-3
Qayum MBadawy ACook JJacob B(2017)DyAdHyTMProceedings of the International Symposium on Memory Systems10.1145/3132402.3132442(327-336)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132442
de Carvalho JAraujo GBaldassin AGropp WBeckman PLi ZCazorla F(2017)Revisiting phased transactional memoryProceedings of the International Conference on Supercomputing10.1145/3079079.3079094(1-10)Online publication date: 14-Jun-2017
https://dl.acm.org/doi/10.1145/3079079.3079094
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten