Cited By
View all- Li SHemani A(2014)Case Study: Constraint Programming in a System Level Synthesis FrameworkPrinciples and Practice of Constraint Programming10.1007/978-3-319-10428-7_60(846-861)Online publication date: 2014
A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
Pages 25 - 32
Abstract
This paper presents a code generation method that translates an intermediate Register-Transfer Level (RTL) model of a system into its corresponding VHDL code for ASIC and FPGAs and MATLAB functions for manycores CGRAs. The intermediate representation consists of Function Implementation (FIMPs) and the glue logic. FIMPs are VHDL design units for the ASIC and FPGA implementation styles and MATLAB function templates for the CGRA implementation style, while the glue logic is a compact data structure storing Global Interconnect and Control (GLIC) information.
The automatically generated implementation codes increase the resource usage by 1.5% on the average while reducing total design effort by two orders of magnitudes.
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Index Terms
- A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
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Published In
June 2013
71 pages
ISBN:9781450320634
DOI:10.1145/2489068
- General Chairs:
- Masoud Daneshtalab,
- Ahmed Hemani,
- Maurizio Palesi
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- Univ. Turku: University of Turku
- KTH (The Royal Institute of Technology), Sweden
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Association for Computing Machinery
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Published: 24 June 2013
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MES '13
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MES '13 Paper Acceptance Rate 5 of 21 submissions, 24%;
Overall Acceptance Rate 5 of 21 submissions, 24%
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View all- Li SHemani A(2014)Case Study: Constraint Programming in a System Level Synthesis FrameworkPrinciples and Practice of Constraint Programming10.1007/978-3-319-10428-7_60(846-861)Online publication date: 2014
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