skip to main content
10.1145/2489068.2489072acmotherconferencesArticle/Chapter ViewAbstractPublication PagesmesConference Proceedingsconference-collections
research-article

A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA

Published: 24 June 2013 Publication History

Abstract

This paper presents a code generation method that translates an intermediate Register-Transfer Level (RTL) model of a system into its corresponding VHDL code for ASIC and FPGAs and MATLAB functions for manycores CGRAs. The intermediate representation consists of Function Implementation (FIMPs) and the glue logic. FIMPs are VHDL design units for the ASIC and FPGA implementation styles and MATLAB function templates for the CGRA implementation style, while the glue logic is a compact data structure storing Global Interconnect and Control (GLIC) information.
The automatically generated implementation codes increase the resource usage by 1.5% on the average while reducing total design effort by two orders of magnitudes.

References

[1]
A. V. Aho, M. S. Lam, R. Sethi, and J. D. Ullman, Compilers: Principles, Techniques, & Tools. Pearson/Addison Wesley, 2007.
[2]
P. R. Panda, "SystemC - A Modeling Platform Supporting Multiple Design Abstractions," in The 14th International Symposium on System Synthesis, 2001, pp. 75--80.
[3]
S. Li, N. Farahini, and A. Hemani, "Global Control and Storage Synthesis for a System Level Synthesis Approach," in The 21st Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2013.
[4]
C. Moler. (2006, Jan.) The Growth of MATLAB and The MathWorks over Two Decades. {Online}. Available: http://www.mathworks.com
[5]
J. Fahimeh, S. Li, and A. Hemani, "Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture," in the 14th Euromicro Conference on Digital System Design (DSD), 2011.
[6]
E. Lee and D. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, Sept. 1987.
[7]
M. A. Shami, "Dynamically Reconfigurable Resource Array," Ph.D. dissertation, KTH, 2012.
[8]
O. Malik, A. Hemani, and M. A. Shami, "A Library Development Framework for a Coarse Grain Reconfigurable Architecture," in the 24th International Conference on VLSI Design, 2011.
[9]
M. A. Shami and A. Hemani, "Partially Reconfigurable Interconnection Network for Dynamically Reprogrammable Resource Array," in The IEEE 8th International Conference on ASIC. IEEE, 2009, pp. 122--125.
[10]
M. A. Shami and A. Hemani, "Address Generation Scheme for a Coarse Grain Reconfigurable Architecture," in IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2011, pp. 17--24.
[11]
M. A. Shami and A. Hemani, "Control Scheme for a CGRA," in The 22nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE, 2010, pp. 17--24.
[12]
C. Pohl, C. Paiz, and M. Porrmann, "vMAGIC - Automatic Code Generation for VHDL," International Journal of Reconfigurable Computing, 2009.
[13]
S. Li, G. Chen, and A. Hemani, "A Code Reuse Method for Many-Core Coarse-Grained Reconfigurable Architecture Function Library Development," in The 13th International Symposium on Integrated Circuits (ISIC). IEEE, 2011, pp. 512--515.
[14]
Y. Joo and N. McKeown, "Doubling Memory Bandwidth for Network Buffers," in the 17th Annual Joint Conference of the IEEE Computer and Communications Societies, 1998.
[15]
A. T. Abdel-Hamid, M. Zaki, and S. Tahar, "A Tool Converting Finite State Machine to VHDL," in Canadian Conference on Electrical and Computer Engineering, vol. 4, 2004, pp. 1907--1910 Vol.4.
[16]
CRASIC: Customisation of Coarse Grain Reconfigurable Architectures. https://drra.wikispaces.com/CRASIC+Project.

Cited By

View all
  • (2014)Case Study: Constraint Programming in a System Level Synthesis FrameworkPrinciples and Practice of Constraint Programming10.1007/978-3-319-10428-7_60(846-861)Online publication date: 2014

Index Terms

  1. A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Other conferences
      MES '13: Proceedings of the First International Workshop on Many-core Embedded Systems
      June 2013
      71 pages
      ISBN:9781450320634
      DOI:10.1145/2489068
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      • Univ. Turku: University of Turku
      • KTH (The Royal Institute of Technology), Sweden

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 24 June 2013

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. code generation
      2. function implementation
      3. global interconnect and control
      4. system-level synthesis

      Qualifiers

      • Research-article

      Conference

      MES '13
      Sponsor:
      • Univ. Turku

      Acceptance Rates

      MES '13 Paper Acceptance Rate 5 of 21 submissions, 24%;
      Overall Acceptance Rate 5 of 21 submissions, 24%

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)2
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 28 Feb 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2014)Case Study: Constraint Programming in a System Level Synthesis FrameworkPrinciples and Practice of Constraint Programming10.1007/978-3-319-10428-7_60(846-861)Online publication date: 2014

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media